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| author | 2014-03-28 13:02:49 +0000 | |
|---|---|---|
| committer | 2014-03-28 13:02:50 +0000 | |
| commit | 6d65a2fae299e3ff4597c668e0cae4f1d3a47694 (patch) | |
| tree | a0d856cfbfd6d94ac2f3290491a24545838e31e6 | |
| parent | ad174d1b54bf2fa477bec71a0ca93595f54b8fe9 (diff) | |
| parent | 217fe73a6c2f3ec44dc52c85c8a101313d048f04 (diff) | |
Merge "Annotate Dalvik VR access as both use and def if we use it in this way"
| -rw-r--r-- | compiler/dex/quick/x86/int_x86.cc | 8 | ||||
| -rw-r--r-- | compiler/dex/quick/x86/utility_x86.cc | 1 |
2 files changed, 9 insertions, 0 deletions
diff --git a/compiler/dex/quick/x86/int_x86.cc b/compiler/dex/quick/x86/int_x86.cc index 37b2b37b45..851f4481a6 100644 --- a/compiler/dex/quick/x86/int_x86.cc +++ b/compiler/dex/quick/x86/int_x86.cc @@ -1179,10 +1179,14 @@ void X86Mir2Lir::GenLongArith(RegLocation rl_dest, RegLocation rl_src, Instructi LIR *lir = NewLIR3(x86op, r_base, displacement + LOWORD_OFFSET, rl_src.reg.GetLowReg()); AnnotateDalvikRegAccess(lir, (displacement + LOWORD_OFFSET) >> 2, + true /* is_load */, true /* is64bit */); + AnnotateDalvikRegAccess(lir, (displacement + LOWORD_OFFSET) >> 2, false /* is_load */, true /* is64bit */); x86op = GetOpcode(op, rl_dest, rl_src, true); lir = NewLIR3(x86op, r_base, displacement + HIWORD_OFFSET, rl_src.reg.GetHighReg()); AnnotateDalvikRegAccess(lir, (displacement + HIWORD_OFFSET) >> 2, + true /* is_load */, true /* is64bit */); + AnnotateDalvikRegAccess(lir, (displacement + HIWORD_OFFSET) >> 2, false /* is_load */, true /* is64bit */); FreeTemp(rl_src.reg); } @@ -1679,12 +1683,16 @@ void X86Mir2Lir::GenLongImm(RegLocation rl_dest, RegLocation rl_src, Instruction X86OpCode x86op = GetOpcode(op, rl_dest, false, val_lo); LIR *lir = NewLIR3(x86op, r_base, displacement + LOWORD_OFFSET, val_lo); AnnotateDalvikRegAccess(lir, (displacement + LOWORD_OFFSET) >> 2, + true /* is_load */, true /* is64bit */); + AnnotateDalvikRegAccess(lir, (displacement + LOWORD_OFFSET) >> 2, false /* is_load */, true /* is64bit */); } if (!IsNoOp(op, val_hi)) { X86OpCode x86op = GetOpcode(op, rl_dest, true, val_hi); LIR *lir = NewLIR3(x86op, r_base, displacement + HIWORD_OFFSET, val_hi); AnnotateDalvikRegAccess(lir, (displacement + HIWORD_OFFSET) >> 2, + true /* is_load */, true /* is64bit */); + AnnotateDalvikRegAccess(lir, (displacement + HIWORD_OFFSET) >> 2, false /* is_load */, true /* is64bit */); } return; diff --git a/compiler/dex/quick/x86/utility_x86.cc b/compiler/dex/quick/x86/utility_x86.cc index 013c40b99d..bb5d387bd5 100644 --- a/compiler/dex/quick/x86/utility_x86.cc +++ b/compiler/dex/quick/x86/utility_x86.cc @@ -368,6 +368,7 @@ LIR* X86Mir2Lir::OpMemReg(OpKind op, RegLocation rl_dest, int r_value) { break; } LIR *l = NewLIR3(opcode, rX86_SP, displacement, r_value); + AnnotateDalvikRegAccess(l, displacement >> 2, true /* is_load */, false /* is_64bit */); AnnotateDalvikRegAccess(l, displacement >> 2, false /* is_load */, false /* is_64bit */); return l; } |