riscv64: small refactors

(1) setup
  lunch aosp_riscv64-trunk-userdebug

  export ART_TEST_SSH_USER=ubuntu
  export ART_TEST_SSH_HOST=localhost
  export ART_TEST_SSH_PORT=10001
  export ART_TEST_ON_VM=true

  . art/tools/buildbot-utils.sh
  art/tools/buildbot-build.sh --target

  # Create, boot and configure the VM.
  art/tools/buildbot-vm.sh create
  art/tools/buildbot-vm.sh boot
  art/tools/buildbot-vm.sh setup-ssh  # password: 'ubuntu'

  art/tools/buildbot-cleanup-device.sh
  art/tools/buildbot-setup-device.sh
  art/tools/buildbot-sync.sh

(2) test
  art/test.py --target -r --no-prebuild --ndebug --64  -j 12 --cdex-none --interpreter

Test: Run these opcodes against all interpreter
tests on a Linux RISC-V VM.

Test: Cuttlefish boot

Bug: 283082047
Change-Id: I44a67ce80ee2cea2533ce7b6e0975a4063d722af

7 files changed, 51 insertions, 52 deletions

diff --git a/runtime/interpreter/mterp/riscv64/array.S b/runtime/interpreter/mterp/riscv64/array.S
index 81171ea6b8..f4d92f1c8b 100644
--- a/runtime/interpreter/mterp/riscv64/array.S
+++ b/runtime/interpreter/mterp/riscv64/array.S
@@ -86,35 +86,35 @@
    beqz $array, $null_label
 
    srliw $index, $index, 8         // index := CC
-%  get_vreg(index, index, is_unsigned=True)  # index := fp[CC], zext for bounds check
+%  get_vreg(index, index)          # index := fp[CC]
    lw $length, MIRROR_ARRAY_LENGTH_OFFSET($array)  // length (signed 32b)
-   bge $index, $length, $oob_label
+   bgeu $index, $length, $oob_label  // Unsigned comparison also catches negative index.
 
 
 // aget vAA, vBB, vCC
 // Format 23x: AA|44 CC|BB
 // vAA := vBB[vCC]
 %def op_aget(width=32, zext=False):
-%  array_prelude(array="t0", index="t1", length="t2", null_label=f".L{opcode}_null", oob_label=f".L{opcode}_oob")
-       // t0 := vBB array object, t1 := vCC zext index, t2 := array length
+%  array_prelude(array="t0", index="a0", length="a1", null_label=f".L{opcode}_null", oob_label=f".L{opcode}_oob")
+       // t0 := vBB array object, a0 := vCC index, a1 := array length
 
 %  if width == 8 and zext:
-     add t0, t1, t0
+     add t0, a0, t0
      lbu t0, MIRROR_BOOLEAN_ARRAY_DATA_OFFSET(t0)
 %  elif width == 8:
-     add t0, t1, t0
+     add t0, a0, t0
      lb t0, MIRROR_BYTE_ARRAY_DATA_OFFSET(t0)
 %  elif width == 16 and zext:
-     sh1add t0, t1, t0
+     sh1add t0, a0, t0
      lhu t0, MIRROR_CHAR_ARRAY_DATA_OFFSET(t0)
 %  elif width == 16:
-     sh1add t0, t1, t0
+     sh1add t0, a0, t0
      lh t0, MIRROR_SHORT_ARRAY_DATA_OFFSET(t0)
 %  elif width == 32:
-     sh2add t0, t1, t0
+     sh2add t0, a0, t0
      lw t0, MIRROR_INT_ARRAY_DATA_OFFSET(t0)
 %  elif width == 64:
-     sh3add t0, t1, t0
+     sh3add t0, a0, t0
      ld t0, MIRROR_WIDE_ARRAY_DATA_OFFSET(t0)
 %  else:
 %    assert False, width
@@ -130,8 +130,6 @@
 .L${opcode}_null:
    tail common_errNullObject
 .L${opcode}_oob:
-   sext.w a0, t1
-   mv a1, t2
    tail common_errArrayIndex  // args a0 (index), a1 (length)
 
 
@@ -144,10 +142,10 @@
 // aget-object vAA, vBB, vCC
 // Format 23x: AA|46 CC|BB
 %def op_aget_object():
-%  array_prelude(array="t0", index="t1", length="t2", null_label=f".L{opcode}_null", oob_label=f".L{opcode}_oob")
-       // t0 := vBB array object, t1 := vCC zext index, t2 := array length
+%  array_prelude(array="t0", index="a0", length="a1", null_label=f".L{opcode}_null", oob_label=f".L{opcode}_oob")
+       // t0 := vBB array object, a0 := vCC index, a1 := array length
 
-   sh2add t0, t1, t0
+   sh2add t0, a0, t0
    lwu a0, MIRROR_OBJECT_ARRAY_DATA_OFFSET(t0)
        // a0 := *(array obj + data offset + idx * elem_size)
    UNPOISON_HEAP_REF a0
@@ -166,8 +164,6 @@
 .L${opcode}_null:
    tail common_errNullObject
 .L${opcode}_oob:
-   sext.w a0, t1
-   mv a1, t2
    tail common_errArrayIndex  // args a0 (index), a1 (length)
 
 
diff --git a/runtime/interpreter/mterp/riscv64/control_flow.S b/runtime/interpreter/mterp/riscv64/control_flow.S
index 2de4ce4b47..3c8a06267c 100644
--- a/runtime/interpreter/mterp/riscv64/control_flow.S
+++ b/runtime/interpreter/mterp/riscv64/control_flow.S
@@ -9,20 +9,20 @@
 // Clobbers: t0
 %def op_return(is_object=False, is_void=False, is_wide=False):
 %  if is_void:
-      // Thread fence for constructor
-      fence w, w
+     // Thread fence for constructor
+     fence w, w
 %  else:
-      srliw t0, xINST, 8  // t0 := AA
+     srliw t0, xINST, 8  // t0 := AA
 %    if is_wide:
-        GET_VREG_WIDE a0, t0  // a0 := fp[AA:AA+1]
-        // The method may return to compiled code, so also place result in fa0.
-        fmv.d.x fa0, a0
+       GET_VREG_WIDE a0, t0  // a0 := fp[AA:AA+1]
+       // The method may return to compiled code, so also place result in fa0.
+       fmv.d.x fa0, a0
 %    elif is_object:
-        GET_VREG_OBJECT a0, t0  // a0 := refs[AA]
+       GET_VREG_OBJECT a0, t0  // a0 := refs[AA]
 %    else:
-%       get_vreg("a0", "t0")    #  a0 := fp[AA]
-        // The method may return to compiled code, so also place result in fa0.
-        fmv.w.x fa0, a0
+%      get_vreg("a0", "t0")    #  a0 := fp[AA]
+       // The method may return to compiled code, so also place result in fa0.
+       fmv.w.x fa0, a0
 %#:
 
    CFI_REMEMBER_STATE
diff --git a/runtime/interpreter/mterp/riscv64/floating_point.S b/runtime/interpreter/mterp/riscv64/floating_point.S
index 937808a5bc..f7bdd69eb5 100644
--- a/runtime/interpreter/mterp/riscv64/floating_point.S
+++ b/runtime/interpreter/mterp/riscv64/floating_point.S
@@ -125,7 +125,7 @@
 %  elif src == "l":
      GET_VREG_WIDE t1, t0     // t1 := fp[B]
 %  elif src == "s":
-%    get_vreg_float("ft0", "t0") #  ft0 := fp[B]
+%    get_vreg_float("ft0", "t0")  #  ft0 := fp[B]
 %  elif src == "d":
      GET_VREG_DOUBLE ft0, t0  // ft0 := fp[B]
 %  else:
@@ -148,7 +148,7 @@
 %  elif dst == "l":
      SET_VREG_WIDE t1, t2, z0=t0     // fp[A] := t1
 %  elif dst == "s":
-%    set_vreg_float("ft0", "t2", z0="t0") # fp[A] := ft0
+%    set_vreg_float("ft0", "t2", z0="t0")  # fp[A] := ft0
 %  elif dst == "d":
      SET_VREG_DOUBLE ft0, t2, z0=t0  // fp[B] := ft0
 %  else:
diff --git a/runtime/interpreter/mterp/riscv64/invoke.S b/runtime/interpreter/mterp/riscv64/invoke.S
index f606f95f6d..75229dc79a 100644
--- a/runtime/interpreter/mterp/riscv64/invoke.S
+++ b/runtime/interpreter/mterp/riscv64/invoke.S
@@ -693,7 +693,7 @@
 
    srliw $z0, xINST, 12              // z0 := A
 %  if arg_start == "0":
-     beqz $z0, .L${uniq}_simple_done // A = 0: no further args.
+     beqz $z0, .L${uniq}_simple_done  // A = 0: no further args.
 %#:
    li $z1, 2
    blt $z0, $z1, .L${uniq}_simple_1  // A = 1
@@ -1495,7 +1495,7 @@
      andi $z0, $v_fedc, 0xF   // z0 := C
 %    get_vreg(z1, z0)         #  z1 := xFP[C]
      sw $z1, (0*4)($z3)       // fp[C] := z1
-     GET_VREG_OBJECT $z0, $z0 // z0 := xREFS[C]
+     GET_VREG_OBJECT $z0, $z0  // z0 := xREFS[C]
      sw $z0, (0*4)($z2)       // refs[C] := z0
 %#:
 .L${uniq}_arg_done:
diff --git a/runtime/interpreter/mterp/riscv64/main.S b/runtime/interpreter/mterp/riscv64/main.S
index d7aeea9a5a..b799380a04 100644
--- a/runtime/interpreter/mterp/riscv64/main.S
+++ b/runtime/interpreter/mterp/riscv64/main.S
@@ -346,7 +346,7 @@ END \name
 // Put "%def" definitions after ".macro" definitions for proper expansion. %def is greedy.
 
 // Typed read, defaults to 32-bit read
-// Note: Incorrect for an object ref; it requires LWU, or LW;ZEXT.W.
+// Note: An object ref requires LWU, or LW;ZEXT.W.
 // Clobbers: \reg
 // Safe if \reg == \vreg.
 %def get_vreg(reg, vreg, width=32, is_wide=False, is_unsigned=False):
diff --git a/runtime/interpreter/mterp/riscv64/object.S b/runtime/interpreter/mterp/riscv64/object.S
index f2de309930..7c8e10a6df 100644
--- a/runtime/interpreter/mterp/riscv64/object.S
+++ b/runtime/interpreter/mterp/riscv64/object.S
@@ -212,7 +212,7 @@
 // iput vA, vB, field@CCCC
 // Format 22c: B|A|59 CCCC
 // vB.field := vA
-%def op_iput(width=32, zext=False):
+%def op_iput(width=32):
    srliw s7, xINST, 12     // s7 := B
    srliw s8, xINST, 8
    andi s8, s8, 0xF        // s8 := A
@@ -349,7 +349,7 @@
 // iput-boolean vA, vB, field@CCCC
 // Format 22c: B|A|5c CCCC
 %def op_iput_boolean():
-%  op_iput(width=8, zext=True)
+%  op_iput(width=8)
 
 
 // iput-byte vA, vB, field@CCCC
@@ -361,7 +361,7 @@
 // iput-char vA, vB, field@CCCC
 // Format 22c: B|A|5e CCCC
 %def op_iput_char():
-%  op_iput(width=16, zext=True)
+%  op_iput(width=16)
 
 
 // iput-short vA, vB, field@CCCC
@@ -707,7 +707,7 @@
    add $z0, $z0, a0  // z0 := field addr, after possible a0 update
    // Ensure the volatile store is released.
    // \value must NOT be the destination register, the destination gets clobbered!
-   // For refs, \value's original value is used in the write barrier below.
+   // \value's original value is used in the write barrier below.
    POISON_HEAP_REF $value  // Poisoning maps null to null for the null check in write barrier.
    amoswap.w.rl zero, $value, ($z0)
 %  object_write_barrier(value=value, holder="a0", z0=z0, z1=z1, uniq=f"slow_{opcode}")
diff --git a/runtime/interpreter/mterp/riscv64/other.S b/runtime/interpreter/mterp/riscv64/other.S
index 3d27822ef0..15f1d9d92d 100644
--- a/runtime/interpreter/mterp/riscv64/other.S
+++ b/runtime/interpreter/mterp/riscv64/other.S
@@ -14,17 +14,18 @@
    srliw t1, xINST, 12   // t1 := B
    srliw t2, xINST, 8    // t2 := B|A
 %  if is_object:
-     GET_VREG_OBJECT t1, t1  // t1 := refs[B]
+     // Note: leaves a useful breadcrumb if the reference is corrupted, unlike GET_VREG_OBJECT.
+%    get_vreg("t1", "t1", is_unsigned=True)  # t1 = fp[B], zext
 %  else:
-%    get_vreg("t1", "t1", is_wide=is_wide) # t1 := fp[B]
+%    get_vreg("t1", "t1", is_wide=is_wide)  # t1 := fp[B]
 %#:
    and t2, t2, 0xF       // t2 := A
    FETCH_ADVANCE_INST 1  // advance xPC, load xINST
    GET_INST_OPCODE t3    // t3 holds next opcode
 %  if is_object:
-     SET_VREG_OBJECT t1, t2, z0=t0 // refs[A] := fp[B]
+     SET_VREG_OBJECT t1, t2, z0=t0  // refs[A] := fp[B]
 %  else:
-%    set_vreg("t1", "t2", z0="t0", is_wide=is_wide) # fp[A] := fp[B]
+%    set_vreg("t1", "t2", z0="t0", is_wide=is_wide)  # fp[A] := fp[B]
 %#:
    GOTO_OPCODE t3       // continue to next
 
@@ -34,16 +35,17 @@
    FETCH t1, count=1     // t1 := BBBB
    srliw t2, xINST, 8    // t2 := AA
 %  if is_object:
-     GET_VREG_OBJECT t1, t1  // t1 := refs[BBBB]
+     // Note: leaves a useful breadcrumb if the reference is corrupted, unlike GET_VREG_OBJECT.
+%    get_vreg("t1", "t1", is_unsigned=True)  # t1 = fp[BBBB], zext
 %  else:
-%    get_vreg("t1", "t1", is_wide=is_wide) # t1 := fp[BBBB]
+%    get_vreg("t1", "t1", is_wide=is_wide)  # t1 := fp[BBBB]
 %#:
    FETCH_ADVANCE_INST 2  // advance xPC, load xINST
    GET_INST_OPCODE t3    // t3 := next opcode
 %  if is_object:
-     SET_VREG_OBJECT t1, t2, z0=t0 // refs[AA] := fp[BBBB]
+     SET_VREG_OBJECT t1, t2, z0=t0  // refs[AA] := fp[BBBB]
 %  else:
-%    set_vreg("t1", "t2", z0="t0", is_wide=is_wide) # fp[AA] := fp[BBBB]
+%    set_vreg("t1", "t2", z0="t0", is_wide=is_wide)  # fp[AA] := fp[BBBB]
 %#:
    GOTO_OPCODE t3        // continue to next
 
@@ -53,16 +55,17 @@
    FETCH t1, count=2     // t1 := BBBB
    FETCH t2, count=1     // t2 := AAAA
 %  if is_object:
-     GET_VREG_OBJECT t1, t1  // t1 := refs[BBBB]
+     // Note: leaves a useful breadcrumb if the reference is corrupted, unlike GET_VREG_OBJECT.
+%    get_vreg("t1", "t1", is_unsigned=True)  # t1 = fp[BBBB], zext
 %  else:
-%    get_vreg("t1", "t1", is_wide=is_wide) # t1 := fp[BBBB]
+%    get_vreg("t1", "t1", is_wide=is_wide)  # t1 := fp[BBBB]
 %#:
    FETCH_ADVANCE_INST 3  // advance xPC, load xINST
    GET_INST_OPCODE t3    // t3 := next opcode
 %  if is_object:
-     SET_VREG_OBJECT t1, t2, z0=t0 // refs[AAAA] := fp[BBBB]
+     SET_VREG_OBJECT t1, t2, z0=t0  // refs[AAAA] := fp[BBBB]
 %  else:
-%    set_vreg("t1", "t2", z0="t0", is_wide=is_wide) # fp[AAAA] := fp[BBBB]
+%    set_vreg("t1", "t2", z0="t0", is_wide=is_wide)  # fp[AAAA] := fp[BBBB]
 %#:
    GOTO_OPCODE t3        // continue to next
 
@@ -106,9 +109,9 @@
    FETCH_ADVANCE_INST 1  // advance xPC, load xINST
    GET_INST_OPCODE t2    // t2 := next opcode
 %  if is_object:
-     SET_VREG_OBJECT a0, t1, z0=t0 // refs[AA] := a0
+     SET_VREG_OBJECT a0, t1, z0=t0  // refs[AA] := a0
 %  else:
-%    set_vreg("a0", "t1", z0="t0", is_wide=is_wide) # fp[AA] := a0
+%    set_vreg("a0", "t1", z0="t0", is_wide=is_wide)  # fp[AA] := a0
 %#:
    GOTO_OPCODE t2        // continue to next
 
@@ -143,7 +146,7 @@
    srliw t2, t2, 28        // t2 := A
    FETCH_ADVANCE_INST 1    // advance xPC, load xINST
    GET_INST_OPCODE t3      // t3 holds next opcode
-%  set_vreg("t1", "t2", z0="t0") # fp[A] := sssssssB
+%  set_vreg("t1", "t2", z0="t0")  # fp[A] := sssssssB
    GOTO_OPCODE t3          // continue to next
 
 // const/16 vAA, #+BBBB
@@ -181,7 +184,7 @@
    slliw t1, t1, 16        // t1 := BBBB0000
    FETCH_ADVANCE_INST 2    // advance xPC, load xINST
    GET_INST_OPCODE t3      // t3 := next opcode
-%  set_vreg("t1", "t2", z0="t0") # fp[AA] := BBBB0000
+%  set_vreg("t1", "t2", z0="t0")  # fp[AA] := BBBB0000
    GOTO_OPCODE t3          // continue to next
 
 // const-wide/16 vAA, #+BBBB