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author Andreas Gampe <agampe@google.com> 2015-01-21 02:08:48 +0000
committer Gerrit Code Review <noreply-gerritcodereview@google.com> 2015-01-21 02:08:48 +0000
commit2005655e8c1542f5b7d56ad0ab44872590bc8d07 (patch)
tree6d6f6be798cabf970cbe94df020e16e8de7bb96b
parentb061b894260df6b68bb8a89ed4a1e85e576bb696 (diff)
parent582f541b35f40b75f2629a41259d2162608647d5 (diff)
Merge "ART: Fix arm64 backend"
-rw-r--r--compiler/dex/quick/arm64/utility_arm64.cc8
1 files changed, 6 insertions, 2 deletions
diff --git a/compiler/dex/quick/arm64/utility_arm64.cc b/compiler/dex/quick/arm64/utility_arm64.cc
index 1c29ab8bcb..a331f41aff 100644
--- a/compiler/dex/quick/arm64/utility_arm64.cc
+++ b/compiler/dex/quick/arm64/utility_arm64.cc
@@ -1256,7 +1256,9 @@ LIR* Arm64Mir2Lir::LoadBaseDispBody(RegStorage r_base, int displacement, RegStor
// TODO: cleaner support for index/displacement registers? Not a reference, but must match width.
RegStorage r_scratch = AllocTempWide();
LoadConstantWide(r_scratch, displacement);
- load = LoadBaseIndexed(r_base, r_scratch, r_dest, 0, size);
+ load = LoadBaseIndexed(r_base, r_scratch,
+ (size == kReference) ? As64BitReg(r_dest) : r_dest,
+ 0, size);
FreeTemp(r_scratch);
}
@@ -1344,7 +1346,9 @@ LIR* Arm64Mir2Lir::StoreBaseDispBody(RegStorage r_base, int displacement, RegSto
// Use long sequence.
RegStorage r_scratch = AllocTempWide();
LoadConstantWide(r_scratch, displacement);
- store = StoreBaseIndexed(r_base, r_scratch, r_src, 0, size);
+ store = StoreBaseIndexed(r_base, r_scratch,
+ (size == kReference) ? As64BitReg(r_src) : r_src,
+ 0, size);
FreeTemp(r_scratch);
}