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author Treehugger Robot <treehugger-gerrit@google.com> 2017-02-02 13:30:18 +0000
committer Gerrit Code Review <noreply-gerritcodereview@google.com> 2017-02-02 13:30:19 +0000
commit1e6578a68d6f4499362254bcdeb6bbf55e309ea4 (patch)
tree6f791c3062b7913de230674b022e61d64c79c0b8
parent2cf7d5e53e94ceb2bccb06f251fd3df26e126011 (diff)
parent85885fe630462955e68ed0f2668c1c42e633dfd1 (diff)
Merge "MIPS: Correct instruction alignment."
-rw-r--r--runtime/arch/instruction_set.h8
1 files changed, 4 insertions, 4 deletions
diff --git a/runtime/arch/instruction_set.h b/runtime/arch/instruction_set.h
index 99aea62468..7ef9a7abb5 100644
--- a/runtime/arch/instruction_set.h
+++ b/runtime/arch/instruction_set.h
@@ -68,8 +68,8 @@ static constexpr size_t kArmAlignment = 8;
// ARM64 instruction alignment. This is the recommended alignment for maximum performance.
static constexpr size_t kArm64Alignment = 16;
-// MIPS instruction alignment. MIPS processors require code to be 4-byte aligned.
-// TODO: Can this be 4?
+// MIPS instruction alignment. MIPS processors require code to be 4-byte aligned,
+// but 64-bit literals must be 8-byte aligned.
static constexpr size_t kMipsAlignment = 8;
// X86 instruction alignment. This is the recommended alignment for maximum performance.
@@ -80,8 +80,8 @@ static constexpr size_t kThumb2InstructionAlignment = 2;
static constexpr size_t kArm64InstructionAlignment = 4;
static constexpr size_t kX86InstructionAlignment = 1;
static constexpr size_t kX86_64InstructionAlignment = 1;
-static constexpr size_t kMipsInstructionAlignment = 2;
-static constexpr size_t kMips64InstructionAlignment = 2;
+static constexpr size_t kMipsInstructionAlignment = 4;
+static constexpr size_t kMips64InstructionAlignment = 4;
const char* GetInstructionSetString(InstructionSet isa);