diff --git a/drivers/platform/msm/ipa/ipa_v3/ipa_debugfs.c b/drivers/platform/msm/ipa/ipa_v3/ipa_debugfs.c
index ac14f07..61627f9 100644
--- a/drivers/platform/msm/ipa/ipa_v3/ipa_debugfs.c
+++ b/drivers/platform/msm/ipa/ipa_v3/ipa_debugfs.c
@@ -24,6 +24,7 @@
 #define IPA_MAX_ENTRY_STRING_LEN 500
 #define IPA_MAX_MSG_LEN 4096
 #define IPA_DBG_MAX_RULE_IN_TBL 128
+#define IPA_TSP_OPTION_LEN 16
 #define IPA_DBG_ACTIVE_CLIENT_BUF_SIZE ((IPA3_ACTIVE_CLIENTS_LOG_LINE_LEN \
 	* IPA3_ACTIVE_CLIENTS_LOG_BUFFER_SIZE_LINES) + IPA_MAX_MSG_LEN)
 
@@ -3077,6 +3078,9 @@
 	IPA_DUMP_STATUS_FIELD(frag_hit);
 	IPA_DUMP_STATUS_FIELD(frag_rule);
 	IPA_DUMP_STATUS_FIELD(ttl_dec);
+	IPA_DUMP_STATUS_FIELD(tsp);
+	IPA_DUMP_STATUS_FIELD(ingress_tc);
+	IPA_DUMP_STATUS_FIELD(egress_tc);
 }
 
 static ssize_t ipa_status_stats_read(struct file *file, char __user *ubuf,
@@ -3334,12 +3338,25 @@
 	struct ipa_ioc_tsp_ingress_class_params ingr_tc;
 	struct ipa_ioc_tsp_egress_prod_params egr_ep;
 	struct ipa_ioc_tsp_egress_class_params egr_tc;
+	u32 ingr_tc_base, egr_tc_base, prod_base;
+	void *ingr_tc_mmio, *egr_tc_mmio, *prod_mmio;
+
+
+	/* map IPA SRAM */
 
 	/* Print the global TSP state flags */
 	IPA_ACTIVE_CLIENTS_INC_SIMPLE();
+	ingr_tc_base = ipahal_read_reg(IPA_RAM_INGRESS_POLICER_DB_BASE_ADDR);
+	egr_tc_base = ipahal_read_reg(IPA_RAM_EGRESS_SHAPING_TC_DB_BASE_ADDR);
+	prod_base = ipahal_read_reg(IPA_RAM_EGRESS_SHAPING_PROD_DB_BASE_ADDR);
 	ipahal_read_reg_fields(IPA_STATE_TSP, &state_tsp);
 	ipahal_read_reg_fields(IPA_STATE_QMNGR_QUEUE_NONEMPTY, &qm_non_empty);
-	IPA_ACTIVE_CLIENTS_DEC_SIMPLE();
+	ingr_tc_mmio = ioremap(ipa3_ctx->ipa_wrapper_base + ingr_tc_base,
+		ipa3_ctx->tsp.ingr_tc_tbl.size);
+	egr_tc_mmio = ioremap(ipa3_ctx->ipa_wrapper_base + egr_tc_base,
+		ipa3_ctx->tsp.egr_tc_tbl.size);
+	prod_mmio = ioremap(ipa3_ctx->ipa_wrapper_base + prod_base,
+		ipa3_ctx->tsp.egr_ep_tbl.size);
 
 	if (state_tsp.traffic_shaper_idle)
 		nbytes += scnprintf(dbg_buff + nbytes, IPA_MAX_MSG_LEN - nbytes,
@@ -3372,7 +3389,7 @@
 	nbytes += scnprintf(dbg_buff + nbytes, IPA_MAX_MSG_LEN - nbytes,
 			"TC Index\tMax Rate\tMax Burst\tInclude L2\n");
 	for (i = 1; i <= ipa3_ctx->tsp.ingr_tc_max; i++) {
-		ipahal_tsp_parse_hw_ingr_tc(ipa3_ctx->tsp.ingr_tc_tbl.base, i, &ingr_tc);
+		ipahal_tsp_parse_hw_ingr_tc(ingr_tc_mmio, i, &ingr_tc);
 		nbytes += scnprintf(dbg_buff + nbytes, IPA_MAX_MSG_LEN - nbytes,
 			"%02d:\t\t%u\t\t%u\t\t%u\n",
 			i, ingr_tc.max_rate, ingr_tc.max_burst, ingr_tc.include_l2_len);
@@ -3381,12 +3398,15 @@
 	nbytes += scnprintf(dbg_buff + nbytes, IPA_MAX_MSG_LEN - nbytes,
 			"Egress Producer Table:\n");
 	nbytes += scnprintf(dbg_buff + nbytes, IPA_MAX_MSG_LEN - nbytes,
-			"EP Index\tClient\tMax Rate\tMax Burst\n");
+		"EP Index\tClient\tMax Rate\tMax Burst\tTC low\tTC high\tMaxOut B\t\tMaxOut EN\n");
 	for (i = 0; i < ipa3_ctx->tsp.egr_ep_max; i++) {
-		ipahal_tsp_parse_hw_egr_ep(ipa3_ctx->tsp.egr_ep_tbl.base, i, &egr_ep);
+		ipa_tsp_get_egr_ep(i, &egr_ep);
 		nbytes += scnprintf(dbg_buff + nbytes, IPA_MAX_MSG_LEN - nbytes,
-			"%d:\t\t%d\t%u\t\t%u\n",
-			i, ipa3_ctx->tsp.egr_ep_config[i], egr_ep.max_rate, egr_ep.max_burst);
+			"%d:\t\t%d\t%u\t\t%u\t\t%u\t%u\t%u\t\t%u\n",
+			i, ipa3_ctx->tsp.egr_ep_config[i], egr_ep.max_rate, egr_ep.max_burst,
+			egr_ep.tc_lo, egr_ep.tc_hi,
+			egr_ep.max_out_bytes, egr_ep.policing_by_max_out);
+
 	}
 
 	nbytes += scnprintf(dbg_buff + nbytes, IPA_MAX_MSG_LEN - nbytes,
@@ -3394,30 +3414,275 @@
 	nbytes += scnprintf(dbg_buff + nbytes, IPA_MAX_MSG_LEN - nbytes,
 			"TC Index\tMax Rate\tMax Burst\tG. Rate\tG. Burst\n");
 	for (i = 1; i <= ipa3_ctx->tsp.egr_tc_max; i++) {
-		ipahal_tsp_parse_hw_egr_tc(ipa3_ctx->tsp.egr_tc_tbl.base, i, &egr_tc);
+		ipahal_tsp_parse_hw_egr_tc(egr_tc_mmio, i, &egr_tc);
 		nbytes += scnprintf(dbg_buff + nbytes, IPA_MAX_MSG_LEN - nbytes,
 			"%02d:\t\t%u\t\t%u\t\t%u\t%u\n",
 			i, egr_tc.max_rate, egr_tc.max_burst,
 			egr_tc.guaranteed_rate, egr_tc.guaranteed_burst);
 	}
+	IPA_ACTIVE_CLIENTS_DEC_SIMPLE();
+	if (ingr_tc_mmio)
+		iounmap(ingr_tc_mmio);
+	if (egr_tc_mmio)
+		iounmap(egr_tc_mmio);
+	if (prod_mmio)
+		iounmap(prod_mmio);
 
 	return simple_read_from_buffer(buf, count, ppos, dbg_buff, nbytes);
 }
 
+static int ipa3_tsp_ingress_config_commit(char *sptr)
+{
+	struct ipa_ioc_tsp_ingress_class_params tsp_in_tc;
+	char *token;
+	int ret;
+	u8 index;
+	u16 max_rate, max_burst;
+	u32 include_l2_len;
+
+	token = strsep(&sptr, " ");
+	if (!token)
+		return -EINVAL;
+	if (kstrtou8(token, 0, &index) || index == 0 || index > ipa3_ctx->tsp.ingr_tc_max)
+		return -EINVAL;
+
+	token = strsep(&sptr, " ");
+	if (!token)
+		return -EINVAL;
+	if (kstrtou16(token, 0, &max_rate))
+		return -EINVAL;
+
+	token = strsep(&sptr, " ");
+	if (!token)
+		return -EINVAL;
+	if (kstrtou16(token, 0, &max_burst))
+		return -EINVAL;
+
+	token = strsep(&sptr, " ");
+	if (!token)
+		return -EINVAL;
+	if (kstrtou32(token, 0, &include_l2_len) || include_l2_len > 1)
+		return -EINVAL;
+
+	tsp_in_tc.max_rate = max_rate;
+	tsp_in_tc.max_burst = max_burst;
+	tsp_in_tc.include_l2_len = include_l2_len;
+
+	ret = ipa_tsp_set_ingr_tc(index, &tsp_in_tc);
+	if (ret) {
+		IPAERR("Failed to set ingress Traffic class\n");
+		return ret;
+	}
+
+	ret = ipa_tsp_commit();
+	if (ret) {
+		IPAERR("Failed to commit TSP\n");
+		return ret;
+	}
+
+	return 0;
+}
+
+static int ipa3_tsp_egress_config_commit(char *sptr)
+{
+	struct ipa_ioc_tsp_egress_class_params tsp_e_tc;
+	char *token;
+	int ret;
+	u8 index;
+	u16 max_rate, max_burst ,guaranteed_rate, guaranteed_burst;
+
+	token = strsep(&sptr, " ");
+	if (!token)
+		return -EINVAL;
+	if (kstrtou8(token, 0, &index) || index == 0 || index > ipa3_ctx->tsp.egr_tc_max)
+		return -EINVAL;
+
+	token = strsep(&sptr, " ");
+	if (!token)
+		return -EINVAL;
+	if (kstrtou16(token, 0, &max_rate))
+		return -EINVAL;
+
+	token = strsep(&sptr, " ");
+	if (!token)
+		return -EINVAL;
+	if (kstrtou16(token, 0, &max_burst))
+		return -EINVAL;
+
+	token = strsep(&sptr, " ");
+	if (!token)
+		return -EINVAL;
+	if (kstrtou16(token, 0, &guaranteed_rate))
+		return -EINVAL;
+
+	token = strsep(&sptr, " ");
+	if (!token)
+		return -EINVAL;
+	if (kstrtou16(token, 0, &guaranteed_burst))
+		return -EINVAL;
+
+	tsp_e_tc.max_rate = max_rate;
+	tsp_e_tc.max_burst = max_burst;
+	tsp_e_tc.guaranteed_rate = guaranteed_rate;
+	tsp_e_tc.guaranteed_burst = guaranteed_burst;
+
+	ret = ipa_tsp_set_egr_tc(index, &tsp_e_tc);
+	if (ret) {
+		IPAERR("Failed to set egress Traffic class\n");
+		return ret;
+	}
+
+	ret = ipa_tsp_commit();
+	if (ret) {
+		IPAERR("Failed to commit TSP\n");
+		return ret;
+	}
+
+	return 0;
+}
+
+static int ipa3_tsp_producer_config_commit(char *sptr)
+{
+	struct ipa_ioc_tsp_egress_prod_params tsp_ep;
+	char *token;
+	int ret;
+	u8 index;
+	u16 max_rate, max_burst;
+	u32 max_out_bytes, client_num;
+	u8 tc_lo, tc_hi, policing_by_max_out;
+
+	token = strsep(&sptr, " ");
+	if (!token)
+		return -EINVAL;
+	if (kstrtou32(token, 0, &client_num))
+		return -EINVAL;
+
+	token = strsep(&sptr, " ");
+	if (!token)
+		return -EINVAL;
+	if (kstrtou8(token, 0, &index) || index == 0 || index > ipa3_ctx->tsp.egr_ep_max)
+		return -EINVAL;
+
+	token = strsep(&sptr, " ");
+	if (!token)
+		return -EINVAL;
+	if (kstrtou16(token, 0, &max_rate))
+		return -EINVAL;
+
+	token = strsep(&sptr, " ");
+	if (!token)
+		return -EINVAL;
+	if (kstrtou16(token, 0, &max_burst))
+		return -EINVAL;
+
+	token = strsep(&sptr, " ");
+	if (!token)
+		return -EINVAL;
+	if (kstrtou32(token, 0, &max_out_bytes))
+		return -EINVAL;
+
+	token = strsep(&sptr, " ");
+	if (!token)
+		return -EINVAL;
+	if (kstrtou8(token, 0, &tc_lo))
+		return -EINVAL;
+
+	token = strsep(&sptr, " ");
+	if (!token)
+		return -EINVAL;
+	if (kstrtou8(token, 0, &tc_hi))
+		return -EINVAL;
+
+	token = strsep(&sptr, " ");
+	if (!token)
+		return -EINVAL;
+	if (kstrtou8(token, 0, &policing_by_max_out) || policing_by_max_out > 1)
+		return -EINVAL;
+
+	tsp_ep.client = client_num;
+	tsp_ep.max_rate = max_rate;
+	tsp_ep.max_burst = max_burst;
+	tsp_ep.max_out_bytes = max_out_bytes;
+	tsp_ep.tc_lo = tc_lo;
+	tsp_ep.tc_hi = tc_hi;
+	tsp_ep.policing_by_max_out = policing_by_max_out;
+
+	ret = ipa_tsp_set_egr_ep(index, &tsp_ep);
+	if (ret) {
+		IPAERR("Failed to set TSP Producer\n");
+		return ret;
+	}
+
+	ret = ipa_tsp_commit();
+	if (ret) {
+		IPAERR("Failed to commit TSP\n");
+		return ret;
+	}
+
+	return 0;
+}
+
 static ssize_t ipa3_write_tsp(struct file *file, const char __user *buf,
 			      size_t count, loff_t *ppos) {
 
+	unsigned long missing;
+	char *sptr, *token;
+	char option[IPA_TSP_OPTION_LEN];
 	int ret;
-	u8 option = 0;
 
 	if (count >= sizeof(dbg_buff))
 		return -EFAULT;
 
-	ret = kstrtou8_from_user(buf, count, 0, &option);
-	if(ret)
-		return ret;
+	missing = copy_from_user(dbg_buff, buf, count);
+	if (missing) {
+		IPAERR("Failed to copy data from user\n");
+		return -EFAULT;
+	}
 
-	pr_err("TSP write is not implemented.\n");
+	dbg_buff[count] = '\0';
+
+	sptr = dbg_buff;
+
+	token = strsep(&sptr, " ");
+	if (!token)
+		return -EINVAL;
+
+	strlcpy(option, token, IPA_TSP_OPTION_LEN);
+	if (strnstr(option, "ingress", IPA_TSP_OPTION_LEN)) {
+		ret = ipa3_tsp_ingress_config_commit(sptr);
+		if (ret) {
+			IPAERR("Failed to config and commit Ingress Traffic class");
+			return ret;
+		}
+		IPADBG("Ingress Traffic Class config and commit done.");
+	} else if (strnstr(option, "egress", IPA_TSP_OPTION_LEN)) {
+		ret = ipa3_tsp_egress_config_commit(sptr);
+		if (ret) {
+			IPAERR("Failed to config and commit Egress Traffic class");
+			return ret;
+		}
+		IPADBG("Egress Traffic Class config and commit done.");
+	} else if (strnstr(option, "producer", IPA_TSP_OPTION_LEN)) {
+		ret = ipa3_tsp_producer_config_commit(sptr);
+		if (ret) {
+			IPAERR("Failed to config and commit TSP Producer");
+			return ret;
+		}
+		IPADBG("TSP Producer config and commit done.");
+	} else if (strnstr(option, "reset", IPA_TSP_OPTION_LEN)) {
+		ret = ipa_tsp_reset();
+		if (ret) {
+			IPAERR("Failed to reset TSP");
+			return ret;
+		}
+		IPADBG("Reset TSP done.");
+	} else {
+		IPAERR("TSP command format should be one of the following:\n \
+			ingress <index> <max_rate> <max_burst> <include_l2_len>\n \
+			egress <index> <max rate> <max_burst> <guaranteed_rate> <guaranteed_burst>\n \
+			producer <client num> <index> <max rate> <max_burst> <max_out_bytes> <tc_lo> <tc_hi> <policing_by_max_out>\n \
+			reset\n");
+	}
 
 	return count;
 }
diff --git a/drivers/platform/msm/ipa/ipa_v3/ipa_tsp.c b/drivers/platform/msm/ipa/ipa_v3/ipa_tsp.c
index 7a1f0e1..c2a268a 100644
--- a/drivers/platform/msm/ipa/ipa_v3/ipa_tsp.c
+++ b/drivers/platform/msm/ipa/ipa_v3/ipa_tsp.c
@@ -182,18 +182,45 @@
 
 int ipa_tsp_get_egr_ep(u8 index, struct ipa_ioc_tsp_egress_prod_params *output)
 {
-	u32 regval;
+	u32 regval, prod_base;
 	struct ipa_ep_cfg_prod_cfg prod_cfg;
+	void *prod_mmio;
+
+	if (index >= ipa3_ctx->tsp.egr_ep_max) {
+		IPAERR("Invalid producer index.\n");
+		return -EINVAL;
+	}
+
+	if (ipa3_ctx->tsp.egr_ep_config[index] == IPA_CLIENT_MAX)
+		return 0;
+
+	IPA_ACTIVE_CLIENTS_INC_SIMPLE();
+
+	prod_base = ipahal_read_reg(IPA_RAM_EGRESS_SHAPING_PROD_DB_BASE_ADDR);
+	prod_mmio = ioremap(ipa3_ctx->ipa_wrapper_base + prod_base,
+		ipa3_ctx->tsp.egr_ep_tbl.size);
+	if (!prod_mmio) {
+		IPAERR("Failed to ioremap TSP SRAM\n");
+		return -EFAULT;
+	}
 
 	/* The function is internal only, assuming valid params */
 
-	ipahal_tsp_parse_hw_egr_ep(ipa3_ctx->tsp.egr_ep_tbl.base, index, output);
+	ipahal_tsp_parse_hw_egr_ep(prod_mmio, index, output);
 
 	output->client = ipa3_ctx->tsp.egr_ep_config[index];
 
 	regval = ipahal_read_reg_n_fields(IPA_ENDP_INIT_PROD_CFG_n,
 		ipa3_get_ep_mapping(output->client), (void *)&prod_cfg);
 
+	IPA_ACTIVE_CLIENTS_DEC_SIMPLE();
+	if (prod_mmio)
+		iounmap(prod_mmio);
+
+	if (!prod_cfg.tsp_enable)
+		IPAERR("TSP is not enabled on %s EP %d!\n",
+			ipa_clients_strings[output->client], ipa3_get_ep_mapping(output->client));
+
 	output->max_out_bytes = prod_cfg.max_output_size << 6; // max_output_size*64
 	output->policing_by_max_out = prod_cfg.max_output_size_drop_enable;
 	output->tc_lo = prod_cfg.egress_tc_lowest;
@@ -224,19 +251,35 @@
 
 int ipa_tsp_set_egr_ep(u8 index, const struct ipa_ioc_tsp_egress_prod_params *input)
 {
-	u32 regval, ep_index, ep_tc_mask, new_tc_range_mask;
-	struct ipa_ep_cfg_prod_cfg prod_cfg;
+	int new_ep_index;
+	u32 ep_index, ep_tc_mask, new_tc_range_mask;
+	struct ipa_ep_cfg_aggr aggr_cfg = {0};
+	struct ipa_ep_cfg_prod_cfg prod_cfg = {0};
 	bool cleanup = false;
 
+	if (index >= ipa3_ctx->tsp.egr_ep_max) {
+		IPAERR("Invalid producer index.\n");
+		return -EINVAL;
+	}
+
+	if ((new_ep_index = ipa3_get_ep_mapping(input->client)) == IPA_EP_NOT_ALLOCATED) {
+		IPAERR("Failed getting the producer EP index.\n");
+		return -EINVAL;
+	}
+
+	if (input->max_out_bytes >> 6 > 255) {
+		IPAERR("Invalid max out size: %d bytes. Must be up to 16320 bytes.\n",
+			input->max_out_bytes);
+		return -EINVAL;
+	}
+
 	ep_tc_mask = GENMASK(input->tc_hi, input->tc_lo);
 	new_tc_range_mask = ipa3_ctx->tsp.egr_tc_range_mask;
 
-	ep_index = ipa3_get_ep_mapping(ipa3_ctx->tsp.egr_ep_config[index]);
-	regval = ipahal_read_reg_n_fields(
-		IPA_ENDP_INIT_PROD_CFG_n, ep_index, (void *)&prod_cfg);
-
+	/* Checking for an overlap to clean, if needed */
 	if (ipa3_ctx->tsp.egr_ep_config[index] != IPA_CLIENT_MAX &&
 	    ipa3_ctx->tsp.egr_ep_config[index] != input->client) {
+		ep_index = ipa3_get_ep_mapping(ipa3_ctx->tsp.egr_ep_config[index]);
 		cleanup = true;
 		new_tc_range_mask &= !GENMASK(prod_cfg.egress_tc_highest,prod_cfg.egress_tc_lowest);
 	}
@@ -263,7 +306,8 @@
 	prod_cfg.max_output_size_drop_enable = input->policing_by_max_out;
 	prod_cfg.egress_tc_lowest = input->tc_lo;
 	prod_cfg.egress_tc_highest = input->tc_hi;
-	if (ipa3_cfg_ep_prod_cfg(ipa3_get_ep_mapping(input->client), &prod_cfg) != 0) {
+	if (ipa3_cfg_ep_aggr((u32)new_ep_index, &aggr_cfg) != 0 ||
+	    ipa3_cfg_ep_prod_cfg((u32)new_ep_index, &prod_cfg) != 0) {
 		IPAERR("Failed configuring the producer EP.\n");
 		return -EFAULT;
 	}
@@ -287,9 +331,9 @@
 	 * and only maximal bandwidth rate will be considered.
 	 */
 	if (input->guaranteed_rate || input->guaranteed_burst)
-		ipahal_write_reg_mask(IPA_TSP_EGRESS_POLICING_CFG, 0x1 << index, 0x1 << index);
-	else
 		ipahal_write_reg_mask(IPA_TSP_EGRESS_POLICING_CFG, 0x0, 0x1 << index);
+	else
+		ipahal_write_reg_mask(IPA_TSP_EGRESS_POLICING_CFG, 0x1 << index, 0x1 << index);
 
 	return 0;
 }
diff --git a/drivers/platform/msm/ipa/ipa_v3/ipa_utils.c b/drivers/platform/msm/ipa/ipa_v3/ipa_utils.c
index da22550..cf95db4 100644
--- a/drivers/platform/msm/ipa/ipa_v3/ipa_utils.c
+++ b/drivers/platform/msm/ipa/ipa_v3/ipa_utils.c
@@ -7695,7 +7695,7 @@
 	hw_idx = ipa3_ctx->hw_type_index;
 
 	if (client >= IPA_CLIENT_MAX || client < 0) {
-		IPAERR_RL("Bad client number! client =%d\n", client);
+		IPAERR_RL("Bad client number! client = %d\n", client);
 		return IPA_EP_NOT_ALLOCATED;
 	}
 
diff --git a/drivers/platform/msm/ipa/ipa_v3/ipahal/ipahal_tsp.c b/drivers/platform/msm/ipa/ipa_v3/ipahal/ipahal_tsp.c
index 948ab23..0a2cce7 100644
--- a/drivers/platform/msm/ipa/ipa_v3/ipahal/ipahal_tsp.c
+++ b/drivers/platform/msm/ipa/ipa_v3/ipahal/ipahal_tsp.c
@@ -10,6 +10,9 @@
 #include "ipahal_reg.h"
 #include "ipahal_tsp.h"
 
+/* The frequency is 65536/rate per HPG, but the container is only 16 bits,
+   the below will solve the rate=1 corner case */
+#define RATE_TO_FREQ(x) ((x <= 1) ? 65535 : (65536 / x))
 
 void ipahal_tsp_fill_hw_ingr_tc(const struct ipa_ioc_tsp_ingress_class_params *input,
 	void *table, u8 index)
@@ -30,17 +33,17 @@
 	union ipahal_tsp_egress_prod *hal_egr_ep =
 		(union ipahal_tsp_egress_prod *)table + index;
 
-	if ((index & 0x1)) {
+	if (!(index & 0x1)) {
 		/* even index */
 		hal_egr_ep->even.max_rate = input->max_rate;
-		hal_egr_ep->even.max_freq = 65536 / input->max_rate;
+		hal_egr_ep->even.max_freq = RATE_TO_FREQ(input->max_rate);
 		hal_egr_ep->even.max_burst = input->max_burst;
 		hal_egr_ep->even.max_bucket = input->max_burst;
 		hal_egr_ep->even.last_rtc = 0x0;
 	} else {
 		/* odd index */
 		hal_egr_ep->odd.max_rate = input->max_rate;
-		hal_egr_ep->odd.max_freq = 65536 / input->max_rate;
+		hal_egr_ep->odd.max_freq = RATE_TO_FREQ(input->max_rate);
 		hal_egr_ep->odd.max_burst = input->max_burst;
 		hal_egr_ep->odd.max_bucket = input->max_burst;
 		hal_egr_ep->odd.last_rtc = 0x0;
@@ -58,8 +61,8 @@
 		/* even index */
 		hal_egr_tc->even.guaranteed_rate = input->guaranteed_rate;
 		hal_egr_tc->even.max_rate = input->max_rate;
-		hal_egr_tc->even.guaranteed_freq = 65536 / input->guaranteed_rate;
-		hal_egr_tc->even.max_freq = 65536 / input->max_rate;
+		hal_egr_tc->even.guaranteed_freq = RATE_TO_FREQ(input->guaranteed_rate);
+		hal_egr_tc->even.max_freq = RATE_TO_FREQ(input->max_rate);
 		hal_egr_tc->even.guaranteed_burst = input->guaranteed_burst;
 		hal_egr_tc->even.max_burst = input->max_burst;
 		hal_egr_tc->even.max_bucket = input->max_burst;
@@ -68,8 +71,8 @@
 		/* odd index */
 		hal_egr_tc->odd.guaranteed_rate = input->guaranteed_rate;
 		hal_egr_tc->odd.max_rate = input->max_rate;
-		hal_egr_tc->odd.guaranteed_freq = 65536 / input->guaranteed_rate;
-		hal_egr_tc->odd.max_freq = 65536 / input->max_rate;
+		hal_egr_tc->odd.guaranteed_freq = RATE_TO_FREQ(input->guaranteed_rate);
+		hal_egr_tc->odd.max_freq = RATE_TO_FREQ(input->max_rate);
 		hal_egr_tc->odd.guaranteed_burst = input->guaranteed_burst;
 		hal_egr_tc->odd.max_burst = input->max_burst;
 		hal_egr_tc->odd.max_bucket = input->max_burst;
@@ -116,7 +119,7 @@
 	union ipahal_tsp_egress_prod *hal_egr_ep =
 		(union ipahal_tsp_egress_prod *)table + index;
 
-	if ((index & 0x1)) {
+	if (!(index & 0x1)) {
 		/* even index */
 		output->max_rate = hal_egr_ep->even.max_rate;
 		output->max_burst = hal_egr_ep->even.max_burst;
diff --git a/drivers/platform/msm/ipa/ipa_v3/ipahal/ipahal_tsp_i.h b/drivers/platform/msm/ipa/ipa_v3/ipahal/ipahal_tsp_i.h
index 1ffae65..68319d3 100644
--- a/drivers/platform/msm/ipa/ipa_v3/ipahal/ipahal_tsp_i.h
+++ b/drivers/platform/msm/ipa/ipa_v3/ipahal/ipahal_tsp_i.h
@@ -85,7 +85,7 @@
 };
 
 /**
- * struct ipahal_tsp_egress_class_even - IPA egress traffic-class (even index)
+ * struct ipahal_tsp_egress_class_odd - IPA egress traffic-class (odd index)
  *
  * @last_rtc: For HW use, initialize to 0x0000
  * @reserved: Reserved
@@ -100,7 +100,7 @@
  * @guaranteed_burst: Maximal-burst allowed for guaranteed bandwidth rate (in bytes)
  * @max_burst: Maximal-burst allowed for maximal bandwidth rate (in bytes)
  */
-struct ipahal_tsp_egress_class_even {
+struct ipahal_tsp_egress_class_odd {
 	u16 last_rtc;
 	u16 reserved;
 	u16 guaranteed_bucket;
@@ -114,7 +114,7 @@
 };
 
 /**
- * struct ipahal_tsp_egress_class_odd - IPA egress traffic-class (odd index)
+ * struct ipahal_tsp_egress_class_even - IPA egress traffic-class (even index)
  *
  * @guaranteed_burst: Maximal-burst allowed for guaranteed bandwidth rate (in bytes)
  * @max_burst: Maximal-burst allowed for maximal bandwidth rate (in bytes)
@@ -129,7 +129,7 @@
  * @max_freq: In units of 0.833*usec/64KB, Calculated as:
  * 			 max_freq = 65536/max_rate (always be rounded up)
  */
-struct ipahal_tsp_egress_class_odd {
+struct ipahal_tsp_egress_class_even {
 	u16 guaranteed_burst;
 	u16 max_burst;
 	u16 last_rtc;