Merge "gsi: Add clock voting before IO access in debugfs"
diff --git a/config/dataipa_GKI_ipav4.conf b/config/dataipa_GKI_ipav4.conf
new file mode 100644
index 0000000..075a719
--- /dev/null
+++ b/config/dataipa_GKI_ipav4.conf
@@ -0,0 +1,5 @@
+export CONFIG_GSI=m
+export CONFIG_IPA_CLIENTS_MANAGER=m
+export CONFIG_IPA_WDI_UNIFIED_API=y
+export CONFIG_RMNET_IPA3=y
+export CONFIG_RNDIS_IPA=m
diff --git a/config/dataipa_vendor_ipav4.h b/config/dataipa_vendor_ipav4.h
new file mode 100644
index 0000000..6616a91
--- /dev/null
+++ b/config/dataipa_vendor_ipav4.h
@@ -0,0 +1,10 @@
+/*
+* Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
+*/
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#define CONFIG_GSI 1
+#define CONFIG_RMNET_IPA3 1
+#define CONFIG_RNDIS_IPA 1
+#define CONFIG_IPA_WDI_UNIFIED_API 1
+#define CONFIG_IPA_VENDOR_DLKM 1
diff --git a/dataipa_dlkm_vendor_board.mk b/dataipa_dlkm_vendor_board.mk
index 63c90fa..9dc16a3 100644
--- a/dataipa_dlkm_vendor_board.mk
+++ b/dataipa_dlkm_vendor_board.mk
@@ -9,7 +9,7 @@
endif
ifeq ($(TARGET_DATAIPA_DLKM_ENABLE), true)
-DATA_DLKM_BOARD_PLATFORMS_LIST := taro kalama
+DATA_DLKM_BOARD_PLATFORMS_LIST := taro kalama bengal
ifneq ($(TARGET_BOARD_AUTO),true)
ifeq ($(call is-board-platform-in-list,$(DATA_DLKM_BOARD_PLATFORMS_LIST)),true)
BOARD_VENDOR_KERNEL_MODULES += $(KERNEL_MODULES_OUT)/gsim.ko
diff --git a/drivers/platform/msm/Android.mk b/drivers/platform/msm/Android.mk
index 230ef2b..2520e4b 100644
--- a/drivers/platform/msm/Android.mk
+++ b/drivers/platform/msm/Android.mk
@@ -1,5 +1,5 @@
ifneq ($(TARGET_BOARD_PLATFORM),qssi)
-GSI_DLKM_PLATFORMS_LIST := taro kalama
+GSI_DLKM_PLATFORMS_LIST := taro kalama bengal
ifeq ($(call is-board-platform-in-list, $(GSI_DLKM_PLATFORMS_LIST)),true)
#Make file to create GSI DLKM
diff --git a/drivers/platform/msm/Kbuild b/drivers/platform/msm/Kbuild
index 939ccea..a8eac6a 100644
--- a/drivers/platform/msm/Kbuild
+++ b/drivers/platform/msm/Kbuild
@@ -36,6 +36,16 @@
endif
endif
+ifeq ($(CONFIG_ARCH_KHAJE), y)
+DATAIPADRVTOP = $(srctree)/../../vendor/qcom/opensource/dataipa/drivers/platform/msm
+LINUXINCLUDE += -include $(srctree)/../../vendor/qcom/opensource/dataipa/config/dataipa_vendor_ipav4.h
+include $(srctree)/../../vendor/qcom/opensource/dataipa/config/dataipa_GKI_ipav4.conf
+ifeq ($(CONFIG_LOCALVERSION), "-gki-consolidate")
+include $(srctree)/../../vendor/qcom/opensource/dataipa/config/dataipa_GKI_consolidate.conf
+LINUXINCLUDE += -include $(srctree)/../../vendor/qcom/opensource/dataipa/config/dataipa_debug.h
+endif
+endif
+
#MDMs
ifeq ($(CONFIG_ARCH_SDXLEMUR), y)
LINUXINCLUDE += -include $(srctree)/techpack/dataipa/config/dataipa.h
diff --git a/drivers/platform/msm/gsi/gsi.c b/drivers/platform/msm/gsi/gsi.c
index f8970fe..35d2fe9 100644
--- a/drivers/platform/msm/gsi/gsi.c
+++ b/drivers/platform/msm/gsi/gsi.c
@@ -52,15 +52,6 @@
#define GSI_MSB(num) ((u32)((num & GSI_MSB_MASK) >> 32))
#define GSI_LSB(num) ((u32)(num & GSI_LSB_MASK))
-#define GSI_INST_RAM_FW_VER_OFFSET (0)
-#define GSI_INST_RAM_FW_VER_GSI_3_0_OFFSET (64)
-#define GSI_INST_RAM_FW_VER_HW_MASK (0xFC00)
-#define GSI_INST_RAM_FW_VER_HW_SHIFT (10)
-#define GSI_INST_RAM_FW_VER_FLAVOR_MASK (0x380)
-#define GSI_INST_RAM_FW_VER_FLAVOR_SHIFT (7)
-#define GSI_INST_RAM_FW_VER_FW_MASK (0x7f)
-#define GSI_INST_RAM_FW_VER_FW_SHIFT (0)
-
#define GSI_FC_NUM_WORDS_PER_CHNL_SHRAM (20)
#define GSI_FC_STATE_INDEX_SHRAM (7)
#define GSI_FC_PENDING_MASK (0x00080000)
diff --git a/drivers/platform/msm/gsi/gsi.h b/drivers/platform/msm/gsi/gsi.h
index b4cf68f..1e65d0a 100644
--- a/drivers/platform/msm/gsi/gsi.h
+++ b/drivers/platform/msm/gsi/gsi.h
@@ -36,6 +36,16 @@
#define MAX_CHANNELS_SHARING_EVENT_RING 2
#define MINIDUMP_MASK 0x10000
+#define GSI_INST_RAM_FW_VER_OFFSET (0)
+#define GSI_INST_RAM_FW_VER_GSI_3_0_OFFSET (64)
+#define GSI_INST_RAM_FW_VER_GSI_5_5_OFFSET (66)
+#define GSI_INST_RAM_FW_VER_HW_MASK (0xFC00)
+#define GSI_INST_RAM_FW_VER_HW_SHIFT (10)
+#define GSI_INST_RAM_FW_VER_FLAVOR_MASK (0x380)
+#define GSI_INST_RAM_FW_VER_FLAVOR_SHIFT (7)
+#define GSI_INST_RAM_FW_VER_FW_MASK (0x7f)
+#define GSI_INST_RAM_FW_VER_FW_SHIFT (0)
+
#define GSI_IPC_LOGGING(buf, fmt, args...) \
do { \
if (buf) \
diff --git a/drivers/platform/msm/ipa/ipa_v3/dump/ipa5.0/ipa_hw_common_ex.h b/drivers/platform/msm/ipa/ipa_v3/dump/ipa5.0/ipa_hw_common_ex.h
index 711a5d0..52856a9 100644
--- a/drivers/platform/msm/ipa/ipa_v3/dump/ipa5.0/ipa_hw_common_ex.h
+++ b/drivers/platform/msm/ipa/ipa_v3/dump/ipa5.0/ipa_hw_common_ex.h
@@ -445,7 +445,7 @@
/*
* Total number of channel contexts that need to be saved for APPS
*/
-#define IPA_HW_REG_SAVE_GSI_NUM_CH_CNTXT_A7 20
+#define IPA_HW_REG_SAVE_GSI_NUM_CH_CNTXT_A7 27
/*
* Total number of channel contexts that need to be saved for UC
diff --git a/drivers/platform/msm/ipa/ipa_v3/dump/ipa5.0/ipa_reg_dump.c b/drivers/platform/msm/ipa/ipa_v3/dump/ipa5.0/ipa_reg_dump.c
index f38bd47..456c8ce 100644
--- a/drivers/platform/msm/ipa/ipa_v3/dump/ipa5.0/ipa_reg_dump.c
+++ b/drivers/platform/msm/ipa/ipa_v3/dump/ipa5.0/ipa_reg_dump.c
@@ -1075,15 +1075,25 @@
*/
void ipa_save_gsi_ver(void)
{
+ u32 gsi_fw_ver;
+
if (!ipa3_ctx->do_register_collection_on_crash)
return;
if (ipa3_ctx->ipa_hw_type < IPA_HW_v5_0)
- ipa_reg_save.gsi.fw_ver =
+ gsi_fw_ver =
IPA_READ_1xVECTOR_REG(IPA_GSI_TOP_GSI_INST_RAM_n, 0);
if (ipa3_ctx->ipa_hw_type == IPA_HW_v5_0)
- ipa_reg_save.gsi.fw_ver =
+ gsi_fw_ver =
IPA_READ_1xVECTOR_REG(IPA_GSI_TOP_GSI_INST_RAM_n, 64);
+
+ ipa_reg_save.gsi.fw_ver.raw_version = gsi_fw_ver;
+ ipa_reg_save.gsi.fw_ver.hw_version = (gsi_fw_ver & GSI_INST_RAM_FW_VER_HW_MASK) >>
+ GSI_INST_RAM_FW_VER_HW_SHIFT;
+ ipa_reg_save.gsi.fw_ver.flavor = (gsi_fw_ver & GSI_INST_RAM_FW_VER_FLAVOR_MASK) >>
+ GSI_INST_RAM_FW_VER_FLAVOR_SHIFT;
+ ipa_reg_save.gsi.fw_ver.fw_version = (gsi_fw_ver & GSI_INST_RAM_FW_VER_FW_MASK) >>
+ GSI_INST_RAM_FW_VER_FW_SHIFT;
}
/*
diff --git a/drivers/platform/msm/ipa/ipa_v3/dump/ipa5.0/ipa_reg_dump.h b/drivers/platform/msm/ipa/ipa_v3/dump/ipa5.0/ipa_reg_dump.h
index 3e67d3c..398914f 100644
--- a/drivers/platform/msm/ipa/ipa_v3/dump/ipa5.0/ipa_reg_dump.h
+++ b/drivers/platform/msm/ipa/ipa_v3/dump/ipa5.0/ipa_reg_dump.h
@@ -470,10 +470,31 @@
{ GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 19), \
(u32 *)&ipa_reg_save.gsi.ch_cntxt.a7[19].var_name, \
GEN_REG_ATTR(reg_name) }, \
- { GEN_2xVECTOR_REG_OFST(reg_name, IPA_REG_SAVE_HWP_GSI_EE, 1), \
+ { GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 20), \
+ (u32 *)&ipa_reg_save.gsi.ch_cntxt.a7[20].var_name, \
+ GEN_REG_ATTR(reg_name) }, \
+ { GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 21), \
+ (u32 *)&ipa_reg_save.gsi.ch_cntxt.a7[21].var_name, \
+ GEN_REG_ATTR(reg_name) }, \
+ { GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 22), \
+ (u32 *)&ipa_reg_save.gsi.ch_cntxt.a7[22].var_name, \
+ GEN_REG_ATTR(reg_name) }, \
+ { GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 23), \
+ (u32 *)&ipa_reg_save.gsi.ch_cntxt.a7[23].var_name, \
+ GEN_REG_ATTR(reg_name) }, \
+ { GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 24), \
+ (u32 *)&ipa_reg_save.gsi.ch_cntxt.a7[24].var_name, \
+ GEN_REG_ATTR(reg_name) }, \
+ { GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 25), \
+ (u32 *)&ipa_reg_save.gsi.ch_cntxt.a7[25].var_name, \
+ GEN_REG_ATTR(reg_name) }, \
+ { GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 26), \
+ (u32 *)&ipa_reg_save.gsi.ch_cntxt.a7[26].var_name, \
+ GEN_REG_ATTR(reg_name) }, \
+ { GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_UC_EE, 1), \
(u32 *)&ipa_reg_save.gsi.ch_cntxt.uc[0].var_name, \
GEN_REG_ATTR(reg_name) }, \
- { GEN_2xVECTOR_REG_OFST(reg_name, IPA_REG_SAVE_HWP_GSI_EE, 3), \
+ { GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_UC_EE, 3), \
(u32 *)&ipa_reg_save.gsi.ch_cntxt.uc[1].var_name, \
GEN_REG_ATTR(reg_name) }, \
{ GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_Q6_EE, 0), \
@@ -628,6 +649,30 @@
{ GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 18), \
(u32 *)&ipa_reg_save.gsi.evt_cntxt.a7[18].var_name, \
GEN_REG_ATTR(reg_name) }, \
+ { GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 19), \
+ (u32 *)&ipa_reg_save.gsi.evt_cntxt.a7[19].var_name, \
+ GEN_REG_ATTR(reg_name) }, \
+ { GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 20), \
+ (u32 *)&ipa_reg_save.gsi.evt_cntxt.a7[20].var_name, \
+ GEN_REG_ATTR(reg_name) }, \
+ { GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 21), \
+ (u32 *)&ipa_reg_save.gsi.evt_cntxt.a7[21].var_name, \
+ GEN_REG_ATTR(reg_name) }, \
+ { GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 22), \
+ (u32 *)&ipa_reg_save.gsi.evt_cntxt.a7[22].var_name, \
+ GEN_REG_ATTR(reg_name) }, \
+ { GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 23), \
+ (u32 *)&ipa_reg_save.gsi.evt_cntxt.a7[23].var_name, \
+ GEN_REG_ATTR(reg_name) }, \
+ { GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 24), \
+ (u32 *)&ipa_reg_save.gsi.evt_cntxt.a7[24].var_name, \
+ GEN_REG_ATTR(reg_name) }, \
+ { GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 25), \
+ (u32 *)&ipa_reg_save.gsi.evt_cntxt.a7[25].var_name, \
+ GEN_REG_ATTR(reg_name) }, \
+ { GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 26), \
+ (u32 *)&ipa_reg_save.gsi.evt_cntxt.a7[26].var_name, \
+ GEN_REG_ATTR(reg_name) }, \
{ GEN_2xVECTOR_REG_OFST(reg_name, IPA_REG_SAVE_HWP_GSI_EE, 1), \
(u32 *)&ipa_reg_save.gsi.evt_cntxt.uc[0].var_name, \
GEN_REG_ATTR(reg_name) }, \
@@ -1565,6 +1610,14 @@
ipa_gsi_top_gsi_inst_ram_n;
};
+/* GSI fw version data */
+struct ipa_reg_save_gsi_fw_version_s {
+ u32 raw_version;
+ u32 hw_version;
+ u32 flavor;
+ u32 fw_version;
+};
+
/* GSI General EE register save data struct */
struct ipa_reg_save_gsi_gen_ee_s {
struct gsi_hwio_def_gsi_manager_ee_qos_n_s
@@ -1997,7 +2050,7 @@
/* Top level GSI register save data struct */
struct gsi_regs_save_hierarchy_s {
- u32 fw_ver;
+ struct ipa_reg_save_gsi_fw_version_s fw_ver;
struct ipa_reg_save_gsi_gen_s gen;
struct ipa_reg_save_gsi_gen_ee_s gen_ee[IPA_REG_SAVE_GSI_NUM_EE];
struct ipa_reg_save_gsi_ch_cntxt_s ch_cntxt;
diff --git a/drivers/platform/msm/ipa/ipa_v3/dump/ipa5.5/ipa_hw_common_ex.h b/drivers/platform/msm/ipa/ipa_v3/dump/ipa5.5/ipa_hw_common_ex.h
index d25c1d0..971de85 100644
--- a/drivers/platform/msm/ipa/ipa_v3/dump/ipa5.5/ipa_hw_common_ex.h
+++ b/drivers/platform/msm/ipa/ipa_v3/dump/ipa5.5/ipa_hw_common_ex.h
@@ -444,7 +444,7 @@
/*
* Total number of channel contexts that need to be saved for APPS
*/
-#define IPA_HW_REG_SAVE_GSI_NUM_CH_CNTXT_A7 20
+#define IPA_HW_REG_SAVE_GSI_NUM_CH_CNTXT_A7 25
/*
* Total number of channel contexts that need to be saved for UC
@@ -459,7 +459,7 @@
/*
* Total number of event ring contexts that need to be saved for APPS
*/
-#define IPA_HW_REG_SAVE_GSI_NUM_EVT_CNTXT_A7 27
+#define IPA_HW_REG_SAVE_GSI_NUM_EVT_CNTXT_A7 25
/*
* Total number of event ring contexts that need to be saved for UC
diff --git a/drivers/platform/msm/ipa/ipa_v3/dump/ipa5.5/ipa_reg_dump.c b/drivers/platform/msm/ipa/ipa_v3/dump/ipa5.5/ipa_reg_dump.c
index 17e60ae..6dff39c 100644
--- a/drivers/platform/msm/ipa/ipa_v3/dump/ipa5.5/ipa_reg_dump.c
+++ b/drivers/platform/msm/ipa/ipa_v3/dump/ipa5.5/ipa_reg_dump.c
@@ -985,12 +985,21 @@
*/
void ipa_save_gsi_ver(void)
{
+ u32 gsi_fw_ver;
+
if (!ipa3_ctx->do_register_collection_on_crash)
return;
/* IPA_HW_v5_5 */
- ipa_reg_save.gsi.fw_ver =
- IPA_READ_1xVECTOR_REG(IPA_0_GSI_TOP_GSI_INST_RAM_n, 66);
+ gsi_fw_ver = IPA_READ_1xVECTOR_REG(IPA_0_GSI_TOP_GSI_INST_RAM_n, 66);
+
+ ipa_reg_save.gsi.fw_ver.raw_version = gsi_fw_ver;
+ ipa_reg_save.gsi.fw_ver.hw_version = (gsi_fw_ver & GSI_INST_RAM_FW_VER_HW_MASK) >>
+ GSI_INST_RAM_FW_VER_HW_SHIFT;
+ ipa_reg_save.gsi.fw_ver.flavor = (gsi_fw_ver & GSI_INST_RAM_FW_VER_FLAVOR_MASK) >>
+ GSI_INST_RAM_FW_VER_FLAVOR_SHIFT;
+ ipa_reg_save.gsi.fw_ver.fw_version = (gsi_fw_ver & GSI_INST_RAM_FW_VER_FW_MASK) >>
+ GSI_INST_RAM_FW_VER_FW_SHIFT;
}
/*
diff --git a/drivers/platform/msm/ipa/ipa_v3/dump/ipa5.5/ipa_reg_dump.h b/drivers/platform/msm/ipa/ipa_v3/dump/ipa5.5/ipa_reg_dump.h
index 1ceb3a3..650ed52 100644
--- a/drivers/platform/msm/ipa/ipa_v3/dump/ipa5.5/ipa_reg_dump.h
+++ b/drivers/platform/msm/ipa/ipa_v3/dump/ipa5.5/ipa_reg_dump.h
@@ -443,10 +443,25 @@
{ GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 19), \
(u32 *)&ipa_reg_save.gsi.ch_cntxt.a7[19].var_name, \
GEN_REG_ATTR(reg_name) }, \
- { GEN_2xVECTOR_REG_OFST(reg_name, IPA_REG_SAVE_HWP_GSI_EE, 1), \
+ { GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 20), \
+ (u32 *)&ipa_reg_save.gsi.ch_cntxt.a7[20].var_name, \
+ GEN_REG_ATTR(reg_name) }, \
+ { GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 21), \
+ (u32 *)&ipa_reg_save.gsi.ch_cntxt.a7[21].var_name, \
+ GEN_REG_ATTR(reg_name) }, \
+ { GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 22), \
+ (u32 *)&ipa_reg_save.gsi.ch_cntxt.a7[22].var_name, \
+ GEN_REG_ATTR(reg_name) }, \
+ { GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 23), \
+ (u32 *)&ipa_reg_save.gsi.ch_cntxt.a7[23].var_name, \
+ GEN_REG_ATTR(reg_name) }, \
+ { GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 24), \
+ (u32 *)&ipa_reg_save.gsi.ch_cntxt.a7[24].var_name, \
+ GEN_REG_ATTR(reg_name) }, \
+ { GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_UC_EE, 0), \
(u32 *)&ipa_reg_save.gsi.ch_cntxt.uc[0].var_name, \
GEN_REG_ATTR(reg_name) }, \
- { GEN_2xVECTOR_REG_OFST(reg_name, IPA_REG_SAVE_HWP_GSI_EE, 3), \
+ { GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_UC_EE, 3), \
(u32 *)&ipa_reg_save.gsi.ch_cntxt.uc[1].var_name, \
GEN_REG_ATTR(reg_name) }, \
{ GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_Q6_EE, 0), \
@@ -601,6 +616,24 @@
{ GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 18), \
(u32 *)&ipa_reg_save.gsi.evt_cntxt.a7[18].var_name, \
GEN_REG_ATTR(reg_name) }, \
+ { GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 19), \
+ (u32 *)&ipa_reg_save.gsi.evt_cntxt.a7[19].var_name, \
+ GEN_REG_ATTR(reg_name) }, \
+ { GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 20), \
+ (u32 *)&ipa_reg_save.gsi.evt_cntxt.a7[20].var_name, \
+ GEN_REG_ATTR(reg_name) }, \
+ { GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 21), \
+ (u32 *)&ipa_reg_save.gsi.evt_cntxt.a7[21].var_name, \
+ GEN_REG_ATTR(reg_name) }, \
+ { GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 22), \
+ (u32 *)&ipa_reg_save.gsi.evt_cntxt.a7[22].var_name, \
+ GEN_REG_ATTR(reg_name) }, \
+ { GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 23), \
+ (u32 *)&ipa_reg_save.gsi.evt_cntxt.a7[23].var_name, \
+ GEN_REG_ATTR(reg_name) }, \
+ { GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 24), \
+ (u32 *)&ipa_reg_save.gsi.evt_cntxt.a7[24].var_name, \
+ GEN_REG_ATTR(reg_name) }, \
{ GEN_2xVECTOR_REG_OFST(reg_name, IPA_REG_SAVE_HWP_GSI_EE, 1), \
(u32 *)&ipa_reg_save.gsi.evt_cntxt.uc[0].var_name, \
GEN_REG_ATTR(reg_name) }, \
@@ -1465,6 +1498,14 @@
ipa_dst_rsrc_grp_4567_rsrc_type_cnt_n;
};
+/* GSI fw version data */
+struct ipa_reg_save_gsi_fw_version_s {
+ u32 raw_version;
+ u32 hw_version;
+ u32 flavor;
+ u32 fw_version;
+};
+
/* GSI General register save data struct */
struct ipa_reg_save_gsi_gen_s {
struct gsi_hwio_def_gsi_cfg_s
@@ -1867,7 +1908,7 @@
/* Top level GSI register save data struct */
struct gsi_regs_save_hierarchy_s {
- u32 fw_ver;
+ struct ipa_reg_save_gsi_fw_version_s fw_ver;
struct ipa_reg_save_gsi_gen_s gen;
struct ipa_reg_save_gsi_gen_ee_s gen_ee[IPA_REG_SAVE_GSI_NUM_EE];
struct ipa_reg_save_gsi_ch_cntxt_s ch_cntxt;
diff --git a/drivers/platform/msm/ipa/ipa_v3/ipa.c b/drivers/platform/msm/ipa/ipa_v3/ipa.c
index 273e294..7295f6e 100644
--- a/drivers/platform/msm/ipa/ipa_v3/ipa.c
+++ b/drivers/platform/msm/ipa/ipa_v3/ipa.c
@@ -8427,6 +8427,11 @@
scnprintf(fw_name, ARRAY_SIZE(fw_name), "%s.mdt", sub_sys);
ret = of_property_read_u32_index(dev->of_node, "pas-ids", index,
&pas_id);
+ if(ret) {
+ dev_err(dev, "error %d getting \"pass-ids\" property\n",
+ ret);
+ return ret;
+ }
ret = request_firmware(&fw, fw_name, dev);
if (ret) {
@@ -11210,6 +11215,7 @@
IPADBG("ipa q6 smem size = %u\n", ipa_smem_size);
}
+ ipa3_ctx->ipa_smem_size = ipa_smem_size;
if (ipa3_ctx->platform_type != IPA_PLAT_TYPE_APQ) {
/* map SMEM memory for IPA table accesses */
ret = qcom_smem_alloc(SMEM_MODEM,
diff --git a/drivers/platform/msm/ipa/ipa_v3/ipa_dp.c b/drivers/platform/msm/ipa/ipa_v3/ipa_dp.c
index 470ebda..baf3c7b 100644
--- a/drivers/platform/msm/ipa/ipa_v3/ipa_dp.c
+++ b/drivers/platform/msm/ipa/ipa_v3/ipa_dp.c
@@ -5467,7 +5467,9 @@
/* disable ipa_status */
sys->ep->status.status_en = false;
- if (in->client == IPA_CLIENT_APPS_WAN_COAL_CONS)
+ if (in->client == IPA_CLIENT_APPS_WAN_COAL_CONS ||
+ (in->client == IPA_CLIENT_APPS_WAN_CONS &&
+ ipa3_ctx->ipa_hw_type <= IPA_HW_v4_2))
in->ipa_ep_cfg.aggr.aggr_hard_byte_limit_en = 1;
IPADBG("set aggr_limit %lu\n", (unsigned long) *aggr_byte_limit);
diff --git a/drivers/platform/msm/ipa/ipa_v3/ipa_eth_i.c b/drivers/platform/msm/ipa/ipa_v3/ipa_eth_i.c
index be0ffea..dd90faf 100644
--- a/drivers/platform/msm/ipa/ipa_v3/ipa_eth_i.c
+++ b/drivers/platform/msm/ipa/ipa_v3/ipa_eth_i.c
@@ -719,7 +719,7 @@
return result;
}
-static int ipa_eth_setup_ntn3_gsi_channel(
+static int ipa_eth_setup_ntn_gsi_channel(
struct ipa_eth_client_pipe_info *pipe,
struct ipa3_ep_context *ep)
{
@@ -751,11 +751,8 @@
gsi_evt_ring_props.int_modt = IPA_ETH_NTN_MODT;
/* len / RE_SIZE == len in counts (convert from bytes) */
len = pipe->info.transfer_ring_size;
- /*
- * int_modc = 2 is experiments based best value for tput.
- * we shall use a framework setup in the future.
- */
- gsi_evt_ring_props.int_modc = 2;
+ gsi_evt_ring_props.int_modc = len * IPA_ETH_AQC_MODC_FACTOR /
+ (100 * GSI_EVT_RING_RE_SIZE_16B);
gsi_evt_ring_props.exclusive = true;
gsi_evt_ring_props.err_cb = ipa_eth_gsi_evt_ring_err_cb;
gsi_evt_ring_props.user_data = NULL;
@@ -836,8 +833,15 @@
(u32)((u64)(pipe->info.data_buff_list[0].iova) >> 32);
}
- if (pipe->dir == IPA_ETH_PIPE_DIR_TX)
- ch_scratch.ntn.ioc_mod_threshold = IPA_ETH_NTN_MODT;
+ if (pipe->dir == IPA_ETH_PIPE_DIR_TX) {
+ if (pipe->info.client_info.ntn.ioc_mod_threshold &&
+ pipe->info.client_info.ntn.ioc_mod_threshold < len / GSI_EVT_RING_RE_SIZE_16B) {
+ ch_scratch.ntn.ioc_mod_threshold =
+ pipe->info.client_info.ntn.ioc_mod_threshold;
+ } else {
+ ch_scratch.ntn.ioc_mod_threshold = IPA_ETH_NTN_MODT;
+ }
+ }
result = gsi_write_channel_scratch(ep->gsi_chan_hdl, ch_scratch);
if (result != GSI_STATUS_SUCCESS) {
@@ -1018,7 +1022,7 @@
result = ipa_eth_setup_aqc_gsi_channel(pipe, ep);
break;
case IPA_HW_PROTOCOL_NTN3:
- result = ipa_eth_setup_ntn3_gsi_channel(pipe, ep);
+ result = ipa_eth_setup_ntn_gsi_channel(pipe, ep);
break;
default:
IPAERR("unknown protocol %d\n", prot);
diff --git a/drivers/platform/msm/ipa/ipa_v3/ipa_i.h b/drivers/platform/msm/ipa/ipa_v3/ipa_i.h
index d113b84..6afc5a0 100644
--- a/drivers/platform/msm/ipa/ipa_v3/ipa_i.h
+++ b/drivers/platform/msm/ipa/ipa_v3/ipa_i.h
@@ -2584,6 +2584,7 @@
struct list_head minidump_list_head;
phys_addr_t per_stats_smem_pa;
void *per_stats_smem_va;
+ u32 ipa_smem_size;
};
struct ipa3_plat_drv_res {
diff --git a/drivers/platform/msm/ipa/ipa_v3/ipa_qmi_service.c b/drivers/platform/msm/ipa/ipa_v3/ipa_qmi_service.c
index d70d2e5..49735eb 100644
--- a/drivers/platform/msm/ipa/ipa_v3/ipa_qmi_service.c
+++ b/drivers/platform/msm/ipa/ipa_v3/ipa_qmi_service.c
@@ -718,6 +718,10 @@
req.hw_filter_stats_info.hw_filter_stats_size = IPA_Q6_FNR_STATS_SIZE;
req.hw_filter_stats_info.hw_filter_stats_start_index = IPA_Q6_FNR_START_IDX;
req.hw_filter_stats_info.hw_filter_stats_end_index = IPA_Q6_FNR_END_IDX;
+
+ req.smem_info_valid = true;
+ req.smem_info.size = ipa3_ctx->ipa_smem_size;
+
IPAWANDBG("hw_flt stats: hw_filter_start_address = %u", req.hw_filter_stats_info.hw_filter_stats_start_addr);
IPAWANDBG("hw_flt stats: hw_filter_stats_size = %u", req.hw_filter_stats_info.hw_filter_stats_size);
IPAWANDBG("hw_flt stats: hw_filter_stats_start_index = %u", req.hw_filter_stats_info.hw_filter_stats_start_index);
@@ -758,6 +762,8 @@
req.v4_hash_filter_tbl_start_addr);
IPAWANDBG("v6_hash_filter_tbl_start_addr %d\n",
req.v6_hash_filter_tbl_start_addr);
+ IPAWANDBG("ipa_smem_info.size %d\n",
+ req.smem_info.size);
req_desc.max_msg_len = QMI_IPA_INIT_MODEM_DRIVER_REQ_MAX_MSG_LEN_V01;
req_desc.msg_id = QMI_IPA_INIT_MODEM_DRIVER_REQ_V01;
diff --git a/drivers/platform/msm/ipa/ipa_v3/ipa_utils.c b/drivers/platform/msm/ipa/ipa_v3/ipa_utils.c
index 4fabe64..5a93158 100644
--- a/drivers/platform/msm/ipa/ipa_v3/ipa_utils.c
+++ b/drivers/platform/msm/ipa/ipa_v3/ipa_utils.c
@@ -989,6 +989,8 @@
[IPA_4_7][IPA_QMB_INSTANCE_DDR] = {13, 12, 120},
[IPA_4_9][IPA_QMB_INSTANCE_DDR] = {16, 8, 120},
[IPA_4_11][IPA_QMB_INSTANCE_DDR] = {13, 12, 120},
+ [IPA_5_5][IPA_QMB_INSTANCE_DDR] = {16, 12, 0},
+ [IPA_5_5][IPA_QMB_INSTANCE_PCIE] = {16, 8, 0},
};
enum ipa_tx_instance {
@@ -7531,15 +7533,17 @@
}
/* Configure COAL_MASTER_CFG */
- memset(&master_cfg, 0, sizeof(master_cfg));
- ipahal_read_reg_fields(IPA_COAL_MASTER_CFG, &master_cfg);
- master_cfg.coal_ipv4_id_ignore = ipa3_ctx->coal_ipv4_id_ignore;
- ipahal_write_reg_fields(IPA_COAL_MASTER_CFG, &master_cfg);
+ if(ipa3_ctx->ipa_hw_type >= IPA_HW_v5_5) {
+ memset(&master_cfg, 0, sizeof(master_cfg));
+ ipahal_read_reg_fields(IPA_COAL_MASTER_CFG, &master_cfg);
+ master_cfg.coal_ipv4_id_ignore = ipa3_ctx->coal_ipv4_id_ignore;
+ ipahal_write_reg_fields(IPA_COAL_MASTER_CFG, &master_cfg);
- IPADBG(
- ": coal-ipv4-id-ignore = %s\n",
- master_cfg.coal_ipv4_id_ignore ?
- "True" : "False");
+ IPADBG(
+ ": coal-ipv4-id-ignore = %s\n",
+ master_cfg.coal_ipv4_id_ignore ?
+ "True" : "False");
+ }
ipa_comp_cfg();