Merge "sdm: update AVR states properly during mode switch"
diff --git a/sdm/libs/core/display_base.cpp b/sdm/libs/core/display_base.cpp
index 1b1c0ae..edcc64a 100644
--- a/sdm/libs/core/display_base.cpp
+++ b/sdm/libs/core/display_base.cpp
@@ -1969,6 +1969,7 @@
     return error;
   }
 
+  avoid_qsync_mode_change_ = true;
   active_refresh_rate_ = display_attributes.fps;
 
   return ReconfigureDisplay();
diff --git a/sdm/libs/core/display_base.h b/sdm/libs/core/display_base.h
index a40e986..85acf94 100644
--- a/sdm/libs/core/display_base.h
+++ b/sdm/libs/core/display_base.h
@@ -432,6 +432,7 @@
   uint32_t active_refresh_rate_ = 0;
   bool disable_cwb_idle_fallback_ = false;
   bool allow_tonemap_native_ = false;
+  bool avoid_qsync_mode_change_ = false;
 
  private:
   // Max tolerable power-state-change wait-times in milliseconds.
diff --git a/sdm/libs/core/display_builtin.cpp b/sdm/libs/core/display_builtin.cpp
index 5402d8e..da704f5 100644
--- a/sdm/libs/core/display_builtin.cpp
+++ b/sdm/libs/core/display_builtin.cpp
@@ -389,7 +389,7 @@
 }
 
 void DisplayBuiltIn::UpdateQsyncMode() {
-  if (!hw_panel_info_.qsync_support) {
+  if (!hw_panel_info_.qsync_support || avoid_qsync_mode_change_) {
     return;
   }
 
@@ -921,11 +921,17 @@
   } else if (qsync_mode_ == kQsyncModeOneShotContinuous) {
     // No action needed.
   } else if (qsync_mode_ == kQSyncModeContinuous) {
-    needs_avr_update_ = false;
+      if (!avoid_qsync_mode_change_) {
+        needs_avr_update_ = false;
+      } else if (needs_avr_update_) {
+        validated_ = false;
+        event_handler_->Refresh();
+      }
   } else if (qsync_mode_ == kQSyncModeNone) {
     needs_avr_update_ = false;
   }
 
+  avoid_qsync_mode_change_ = false;
   SetVsyncStatus(true /*Re-enable vsync.*/);
 
   bool notify_idle = enable_qsync_idle_ && (active_qsync_mode_ != kQSyncModeNone) &&
@@ -1047,6 +1053,7 @@
       return error;
     }
 
+    avoid_qsync_mode_change_ = true;
     DisplayBase::ReconfigureDisplay();
 
     if (mode == kModeVideo) {
@@ -1999,6 +2006,7 @@
   }
 
   validated_ = false;
+  avoid_qsync_mode_change_ = true;
   DLOGV("Setting new dynamic bit clk value: %" PRIu64, bit_clk_rate);
   return hw_intf_->SetDynamicDSIClock(bit_clk_rate);
 }