commit a7569461e06d1345944aa6c943e09e7fb11f7430
author Meng Wang <mengw@codeaurora.org> Tue Sep 01 08:30:21 2020 +0800
committer Meng Wang <mengw@codeaurora.org> Tue Sep 01 08:30:21 2020 +0800
tree 6562d6ba69e9b4cdea12c01cdb856793052d5052
parent 9bb076173a7a7fa1e0741d669b6707f396a9d958

config: lahaina: add reset value for missed mixer controls

Add reset value for missed mixer controls for Lahaina devices.

Change-Id: I692fc2945f5c0c817d4d607705eaafd41b2b3d00

configs/lahaina/mixer_paths.xml

diff --git a/configs/lahaina/mixer_paths.xml b/configs/lahaina/mixer_paths.xml
index 16f5725..85ca95e 100644
--- a/configs/lahaina/mixer_paths.xml
+++ b/configs/lahaina/mixer_paths.xml
@@ -366,6 +366,15 @@
     <ctl name="TX_AIF1_CAP Mixer DEC5" value="0" />
     <ctl name="TX_AIF1_CAP Mixer DEC6" value="0" />
     <ctl name="TX_AIF1_CAP Mixer DEC7" value="0" />
+    <ctl name="TX_AIF2_CAP Mixer DEC0" value="0" />
+    <ctl name="TX_AIF2_CAP Mixer DEC0" value="0" />
+    <ctl name="TX_AIF2_CAP Mixer DEC1" value="0" />
+    <ctl name="TX_AIF2_CAP Mixer DEC2" value="0" />
+    <ctl name="TX_AIF2_CAP Mixer DEC3" value="0" />
+    <ctl name="TX_AIF2_CAP Mixer DEC4" value="0" />
+    <ctl name="TX_AIF2_CAP Mixer DEC5" value="0" />
+    <ctl name="TX_AIF2_CAP Mixer DEC6" value="0" />
+    <ctl name="TX_AIF2_CAP Mixer DEC7" value="0" />
     <ctl name="TX DEC0 MUX" value="SWR_MIC" />
     <ctl name="TX DMIC MUX0" value="ZERO" />
     <ctl name="TX SMIC MUX0" value="ZERO" />
@@ -396,6 +405,8 @@
     <ctl name="ADC4 ChMap" value="ZERO" />
     <ctl name="HDR12 MUX" value="NO_HDR12" />
     <ctl name="HDR34 MUX" value="NO_HDR34" />
+    <ctl name="MBHC ChMap" value="ZERO" />
+    <ctl name="BCS Channel" value="CH6" />
     <ctl name="SWR_MIC0 HIFI PortMap" value="ZERO" />
     <ctl name="SWR_MIC1 HIFI PortMap" value="ZERO" />
     <ctl name="SWR_MIC2 HIFI PortMap" value="ZERO" />