commit | fd84d97deecc23b8519f8bc1f384a418bb69181b | [log] [tgz] |
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author | Jon Loeliger <jdl@freescale.com> | Thu Feb 15 11:02:44 2007 -0600 |
committer | Jon Loeliger <jdl@freescale.com> | Thu Feb 15 11:02:44 2007 -0600 |
tree | 769b3cda3edfb526529f5c40984036e1e93033f1 | |
parent | af0278a3a04fabe8349cae89613274da196509ca [diff] |
Add some initial test cases. Add the original simple test case and a case with different based cell values. Correct output asm files as well as stderr is captured. Signed-off-by: Jon Loeliger <jdl@freescale.com>