Revert "Revert "ARM: VIXL32: Add an initial code generator that passes codegen_tests.""
This VIXL32-based code generator is not enabled in the optimizing
compiler by default. Changes in codegen_test.cc test it in parallel with
the existing ARM backend.
This patch provides a base for further work, the new backend will not
be enabled in the optimizing compiler until parity is proven with the
current ARM backend and assembler.
Test: gtest-codegen_test on host and target
This reverts commit 7863a2152865a12ad9593d8caad32698264153c1.
Change-Id: Ia09627bac22e78732ca982d207dc0b00bda435bb
diff --git a/compiler/optimizing/codegen_test.cc b/compiler/optimizing/codegen_test.cc
index 070cbb3..f19faa3 100644
--- a/compiler/optimizing/codegen_test.cc
+++ b/compiler/optimizing/codegen_test.cc
@@ -41,6 +41,7 @@
#include "register_allocator_linear_scan.h"
#include "ssa_liveness_analysis.h"
#include "utils.h"
+#include "utils/arm/assembler_arm_vixl.h"
#include "utils/arm/managed_register_arm.h"
#include "utils/mips/managed_register_mips.h"
#include "utils/mips64/managed_register_mips64.h"
@@ -48,6 +49,7 @@
#ifdef ART_ENABLE_CODEGEN_arm
#include "code_generator_arm.h"
+#include "code_generator_arm_vixl.h"
#endif
#ifdef ART_ENABLE_CODEGEN_arm64
@@ -117,6 +119,28 @@
blocked_register_pairs_[arm::R6_R7] = false;
}
};
+
+// A way to test the VIXL32-based code generator on ARM. This will replace
+// TestCodeGeneratorARM when the VIXL32-based backend replaces the existing one.
+class TestCodeGeneratorARMVIXL : public arm::CodeGeneratorARMVIXL {
+ public:
+ TestCodeGeneratorARMVIXL(HGraph* graph,
+ const ArmInstructionSetFeatures& isa_features,
+ const CompilerOptions& compiler_options)
+ : arm::CodeGeneratorARMVIXL(graph, isa_features, compiler_options) {
+ AddAllocatedRegister(Location::RegisterLocation(arm::R6));
+ AddAllocatedRegister(Location::RegisterLocation(arm::R7));
+ }
+
+ void SetupBlockedRegisters() const OVERRIDE {
+ arm::CodeGeneratorARMVIXL::SetupBlockedRegisters();
+ blocked_core_registers_[arm::R4] = true;
+ blocked_core_registers_[arm::R6] = false;
+ blocked_core_registers_[arm::R7] = false;
+ // Makes pair R6-R7 available.
+ blocked_register_pairs_[arm::R6_R7] = false;
+ }
+};
#endif
#ifdef ART_ENABLE_CODEGEN_x86
@@ -296,6 +320,13 @@
*features_arm.get(),
compiler_options);
}
+
+CodeGenerator* create_codegen_arm_vixl32(HGraph* graph, const CompilerOptions& compiler_options) {
+ std::unique_ptr<const ArmInstructionSetFeatures> features_arm(
+ ArmInstructionSetFeatures::FromCppDefines());
+ return new (graph->GetArena())
+ TestCodeGeneratorARMVIXL(graph, *features_arm.get(), compiler_options);
+}
#endif
#ifdef ART_ENABLE_CODEGEN_arm64
@@ -351,6 +382,7 @@
#ifdef ART_ENABLE_CODEGEN_arm
CodegenTargetConfig(kArm, create_codegen_arm),
CodegenTargetConfig(kThumb2, create_codegen_arm),
+ CodegenTargetConfig(kArm, create_codegen_arm_vixl32),
#endif
#ifdef ART_ENABLE_CODEGEN_arm64
CodegenTargetConfig(kArm64, create_codegen_arm64),