riscv64: don't save TR on stack, set it in `DoLongJump` instead.

TR is the ART thread register, so we know that in `DoLongJump`, which
jumps to managed code, we need to restore TR to `Thread::Current()`.

Test: lunch aosp_riscv64-userdebug && m dist
Change-Id: I2f7fd9be4333f5cbb1745241a61566b6281e9ecb
diff --git a/runtime/arch/riscv64/asm_support_riscv64.h b/runtime/arch/riscv64/asm_support_riscv64.h
index 8406a53..2edc40a 100644
--- a/runtime/arch/riscv64/asm_support_riscv64.h
+++ b/runtime/arch/riscv64/asm_support_riscv64.h
@@ -19,7 +19,7 @@
 
 #include "asm_support.h"
 
-// FS0 - FS11, S0 - S11, RA and ArtMethod*, total 8*(12 + 12 + 1 + 1) = 208
+// FS0 - FS11, S0, S2 - S11, RA, ArtMethod*, padding total 8*(12 + 11 + 1 + 1 + 1) = 208
 #define FRAME_SIZE_SAVE_ALL_CALLEE_SAVES 208
 // FA0 - FA7, A1 - A7, S0, S2 - S11, RA and ArtMethod* total 8*(8 + 7 + 11 + 1 + 1) = 224
 // A0 is excluded as the ArtMethod*, and S1 is excluded as the ART thread register TR.
diff --git a/runtime/arch/riscv64/callee_save_frame_riscv64.h b/runtime/arch/riscv64/callee_save_frame_riscv64.h
index ac88881..3b77e25 100644
--- a/runtime/arch/riscv64/callee_save_frame_riscv64.h
+++ b/runtime/arch/riscv64/callee_save_frame_riscv64.h
@@ -37,10 +37,9 @@
     (1 << art::riscv64::S4) | (1 << art::riscv64::S5) | (1 << art::riscv64::S6) |
     (1 << art::riscv64::S7) | (1 << art::riscv64::S8) | (1 << art::riscv64::S9) |
     (1 << art::riscv64::S10) | (1 << art::riscv64::S11);
-// S1(TR) is included because exception handler checks that the saved TR holds Thread::Current().
 // Stack pointer SP is excluded (although it is callee-saved by calling convention) because it is
 // restored by the code logic and not from a stack frame.
-static constexpr uint32_t kRiscv64CalleeSaveAllSpills = (1 << art::riscv64::S1);
+static constexpr uint32_t kRiscv64CalleeSaveAllSpills = 0;
 // Argument registers except X10/A0 (which contains method pointer).
 static constexpr uint32_t kRiscv64CalleeSaveArgSpills =
     (1 << art::riscv64::A1) | (1 << art::riscv64::A2) | (1 << art::riscv64::A3) |
diff --git a/runtime/arch/riscv64/context_riscv64.cc b/runtime/arch/riscv64/context_riscv64.cc
index ddd079b..b7683f4 100644
--- a/runtime/arch/riscv64/context_riscv64.cc
+++ b/runtime/arch/riscv64/context_riscv64.cc
@@ -139,8 +139,10 @@
   for (size_t i = 0; i < kNumberOfFRegisters; ++i) {
     fprs[i] = fprs_[i] != nullptr ? *fprs_[i] : Riscv64Context::kBadFprBase + i;
   }
-  // Ensure the Thread Register contains the address of the current thread.
-  DCHECK_EQ(reinterpret_cast<uintptr_t>(Thread::Current()), gprs[TR]);
+
+  // Fill in TR (the ART Thread Register) with the address of the current thread.
+  gprs[TR] = reinterpret_cast<uintptr_t>(Thread::Current());
+
   // Tell HWASan about the new stack top.
   __hwasan_handle_longjmp(reinterpret_cast<void*>(gprs[SP]));
   art_quick_do_long_jump(gprs, fprs);