Numerous fixes to MIPS. Basic oatexec works.
- Fixed reversed base and destination reg in genConstString
- Changed compiler to use T9 to hold address to jump to
- Fixed compilation of instruction getting current PC
- Prevented T9 from being used as a compiler temp
- Fixed loadBaseDispBody for long form single loads
- Fixed stack setup for SaveAll callee methods to save rSELF & rSUSPEND
- Added .cpload directive to assembly to regenerate $gp when overwritten
- Fixed passing of extra arguments on the stack to account for space
reserved for $a0-$a3
- Fixed resolution trampoline to properly setup and restore stack
- Created mips stubs for interface trampoline and unresolved direct
method trampoline
Change-Id: I63a3fd0366bdfabdebebf58ec4b8bc9443cec355
diff --git a/src/compiler/codegen/GenCommon.cc b/src/compiler/codegen/GenCommon.cc
index d948d2d..c1d4661 100644
--- a/src/compiler/codegen/GenCommon.cc
+++ b/src/compiler/codegen/GenCommon.cc
@@ -1202,7 +1202,7 @@
#if !defined(TARGET_X86)
int rTgt = loadHelper(cUnit, ENTRYPOINT_OFFSET(pResolveStringFromCode));
#endif
- loadWordDisp(cUnit, rRET0, offset_of_string, rARG0);
+ loadWordDisp(cUnit, rARG0, offset_of_string, rRET0);
loadConstant(cUnit, rARG1, string_idx);
#if defined(TARGET_ARM)
opRegImm(cUnit, kOpCmp, rRET0, 0); // Is resolved?
diff --git a/src/compiler/codegen/mips/ArchFactory.cc b/src/compiler/codegen/mips/ArchFactory.cc
index 4a61efb..f51e722 100644
--- a/src/compiler/codegen/mips/ArchFactory.cc
+++ b/src/compiler/codegen/mips/ArchFactory.cc
@@ -107,9 +107,8 @@
*/
int loadHelper(CompilationUnit* cUnit, int offset)
{
- int tReg = oatAllocTemp(cUnit);
- loadWordDisp(cUnit, rSELF, offset, tReg);
- return tReg;
+ loadWordDisp(cUnit, rSELF, offset, r_T9);
+ return r_T9;
}
void spillCoreRegs(CompilationUnit* cUnit)
diff --git a/src/compiler/codegen/mips/Assemble.cc b/src/compiler/codegen/mips/Assemble.cc
index 8c906cc..f19c1f1 100644
--- a/src/compiler/codegen/mips/Assemble.cc
+++ b/src/compiler/codegen/mips/Assemble.cc
@@ -400,7 +400,7 @@
ENCODING_MAP(kMipsDelta, 0x27e00000,
kFmtBitBlt, 20, 16, kFmtBitBlt, 15, 0, kFmtUnused, 15, 0,
kFmtUnused, -1, -1, IS_QUAD_OP | REG_DEF0 | REG_USE_LR |
- NEEDS_FIXUP, "addiu", "!0r,r_ra,0x!1h(!1d)", 4),
+ NEEDS_FIXUP, "addiu", "!0r,ra,0x!1h(!1d)", 4),
ENCODING_MAP(kMipsDeltaHi, 0x3C000000,
kFmtBitBlt, 20, 16, kFmtBitBlt, 15, 0, kFmtUnused, -1, -1,
kFmtUnused, -1, -1, IS_QUAD_OP | REG_DEF0 | NEEDS_FIXUP,
@@ -409,10 +409,10 @@
kFmtBlt5_2, 16, 21, kFmtBitBlt, 15, 0, kFmtUnused, -1, -1,
kFmtUnused, -1, -1, IS_QUAD_OP | REG_DEF0_USE0 | NEEDS_FIXUP,
"ori", "!0r,!0r,0x!1h(!1d)", 4),
- ENCODING_MAP(kMipsCurrPC, 0x04110020,
+ ENCODING_MAP(kMipsCurrPC, 0x04110001,
kFmtUnused, -1, -1, kFmtUnused, -1, -1, kFmtUnused, -1, -1,
kFmtUnused, -1, -1, NO_OPERAND | IS_BRANCH | REG_DEF_LR,
- "pc2ra", "; r_ra <- .+8", 4),
+ "addiu", "ra,pc,8", 4),
ENCODING_MAP(kMipsSync, 0x0000000f,
kFmtBitBlt, 10, 6, kFmtUnused, -1, -1, kFmtUnused, -1, -1,
kFmtUnused, -1, -1, IS_UNARY_OP,
diff --git a/src/compiler/codegen/mips/Mips32/Factory.cc b/src/compiler/codegen/mips/Mips32/Factory.cc
index ad220f8..63c92eb 100644
--- a/src/compiler/codegen/mips/Mips32/Factory.cc
+++ b/src/compiler/codegen/mips/Mips32/Factory.cc
@@ -31,7 +31,7 @@
static int reservedRegs[] = {r_ZERO, r_AT, r_S0, r_S1, r_K0, r_K1, r_GP, r_SP,
r_RA};
static int coreTemps[] = {r_V0, r_V1, r_A0, r_A1, r_A2, r_A3, r_T0, r_T1, r_T2,
- r_T3, r_T4, r_T5, r_T6, r_T7, r_T8, r_T9};
+ r_T3, r_T4, r_T5, r_T6, r_T7, r_T8};
#ifdef __mips_hard_float
static int fpRegs[] = {r_F0, r_F1, r_F2, r_F3, r_F4, r_F5, r_F6, r_F7,
r_F8, r_F9, r_F10, r_F11, r_F12, r_F13, r_F14, r_F15};
@@ -607,8 +607,8 @@
oatFreeTemp(cUnit, rTmp);
} else {
int rTmp = (rBase == rDest) ? oatAllocFreeTemp(cUnit) : rDest;
- res = loadConstant(cUnit, rTmp, displacement);
- load = newLIR3(cUnit, opcode, rDest, rBase, rTmp);
+ res = opRegRegImm(cUnit, kOpAdd, rTmp, rBase, displacement);
+ load = newLIR3(cUnit, opcode, rDest, 0, rTmp);
if (rTmp != rDest)
oatFreeTemp(cUnit, rTmp);
}
diff --git a/src/compiler/codegen/mips/MipsLIR.h b/src/compiler/codegen/mips/MipsLIR.h
index ab4f844..5e5147a 100644
--- a/src/compiler/codegen/mips/MipsLIR.h
+++ b/src/compiler/codegen/mips/MipsLIR.h
@@ -301,7 +301,7 @@
#define rARG3 r_ARG3
#define rRET0 r_RESULT0
#define rRET1 r_RESULT1
-#define rINVOKE_TGT r_V0
+#define rINVOKE_TGT r_T9
/* Shift encodings */
enum MipsShiftEncodings {