commit f65c7be257b9ec7453b9dc7ffd73e8901403e199
author Nicolas Geoffray <ngeoffray@google.com> Mon Dec 10 20:56:27 2018 +0000
committer Nicolas Geoffray <ngeoffray@google.com> Mon Dec 10 20:56:52 2018 +0000
tree 0fa8cfbebb77d2e7796084721c836b44114bdc97
parent 3a16a8f56e989a13419abb554a6f14a9a35570b7

Revert "RFC: ART: ARM64: Support SDOT/UDOT instructions."

This reverts commit 3a16a8f56e989a13419abb554a6f14a9a35570b7.

Reason for revert: Didn't realize the instruction set on pixel3 is still in progress.

bug: 120778346

Change-Id: Ib9b037d4ff98a9ff2b1db695c036f2a58746e3f3

compiler/optimizing/code_generator_vector_arm64.cc

diff --git a/compiler/optimizing/code_generator_vector_arm64.cc b/compiler/optimizing/code_generator_vector_arm64.cc
index 9506ff8..5a18c1f 100644
--- a/compiler/optimizing/code_generator_vector_arm64.cc
+++ b/compiler/optimizing/code_generator_vector_arm64.cc
@@ -16,7 +16,6 @@
 
 #include "code_generator_arm64.h"
 
-#include "arch/arm64/instruction_set_features_arm64.h"
 #include "mirror/array-inl.h"
 #include "mirror/string.h"
 
@@ -38,14 +37,6 @@
 
 #define __ GetVIXLAssembler()->
 
-// Build-time switch for Armv8.4-a dot product instructions.
-static constexpr bool kArm64EmitDotProdInstructions = true;
-
-// Returns whether dot product instructions should be emitted.
-static bool ShouldEmitDotProductInstructions(const CodeGeneratorARM64* codegen_) {
-  return kArm64EmitDotProdInstructions && codegen_->GetInstructionSetFeatures().HasDotProd();
-}
-
 void LocationsBuilderARM64::VisitVecReplicateScalar(HVecReplicateScalar* instruction) {
   LocationSummary* locations = new (GetGraph()->GetAllocator()) LocationSummary(instruction);
   HInstruction* input = instruction->InputAt(0);
@@ -1294,9 +1285,8 @@
   locations->SetInAt(2, Location::RequiresFpuRegister());
   locations->SetOut(Location::SameAsFirstInput());
 
-  // For Int8 and Uint8 general case we need a temp register.
-  if ((DataType::Size(instruction->InputAt(1)->AsVecOperation()->GetPackedType()) == 1) &&
-      !ShouldEmitDotProductInstructions(codegen_)) {
+  // For Int8 and Uint8 we need a temp register.
+  if (DataType::Size(instruction->InputAt(1)->AsVecOperation()->GetPackedType()) == 1) {
     locations->AddTemp(Location::RequiresFpuRegister());
   }
 }
@@ -1318,32 +1308,25 @@
   switch (inputs_data_size) {
     case 1u: {
       DCHECK_EQ(16u, a->GetVectorLength());
+      VRegister tmp = VRegisterFrom(locations->GetTemp(0));
       if (instruction->IsZeroExtending()) {
-        if (ShouldEmitDotProductInstructions(codegen_)) {
-          __ Udot(acc.V4S(), left.V16B(), right.V16B());
-        } else {
-          VRegister tmp = VRegisterFrom(locations->GetTemp(0));
-          __ Umull(tmp.V8H(), left.V8B(), right.V8B());
-          __ Uaddw(acc.V4S(), acc.V4S(), tmp.V4H());
-          __ Uaddw2(acc.V4S(), acc.V4S(), tmp.V8H());
+        // TODO: Use Armv8.4-A UDOT instruction when it is available.
+        __ Umull(tmp.V8H(), left.V8B(), right.V8B());
+        __ Uaddw(acc.V4S(), acc.V4S(), tmp.V4H());
+        __ Uaddw2(acc.V4S(), acc.V4S(), tmp.V8H());
 
-          __ Umull2(tmp.V8H(), left.V16B(), right.V16B());
-          __ Uaddw(acc.V4S(), acc.V4S(), tmp.V4H());
-          __ Uaddw2(acc.V4S(), acc.V4S(), tmp.V8H());
-        }
+        __ Umull2(tmp.V8H(), left.V16B(), right.V16B());
+        __ Uaddw(acc.V4S(), acc.V4S(), tmp.V4H());
+        __ Uaddw2(acc.V4S(), acc.V4S(), tmp.V8H());
       } else {
-        if (ShouldEmitDotProductInstructions(codegen_)) {
-          __ Sdot(acc.V4S(), left.V16B(), right.V16B());
-        } else {
-          VRegister tmp = VRegisterFrom(locations->GetTemp(0));
-          __ Smull(tmp.V8H(), left.V8B(), right.V8B());
-          __ Saddw(acc.V4S(), acc.V4S(), tmp.V4H());
-          __ Saddw2(acc.V4S(), acc.V4S(), tmp.V8H());
+        // TODO: Use Armv8.4-A SDOT instruction when it is available.
+        __ Smull(tmp.V8H(), left.V8B(), right.V8B());
+        __ Saddw(acc.V4S(), acc.V4S(), tmp.V4H());
+        __ Saddw2(acc.V4S(), acc.V4S(), tmp.V8H());
 
-          __ Smull2(tmp.V8H(), left.V16B(), right.V16B());
-          __ Saddw(acc.V4S(), acc.V4S(), tmp.V4H());
-          __ Saddw2(acc.V4S(), acc.V4S(), tmp.V8H());
-        }
+        __ Smull2(tmp.V8H(), left.V16B(), right.V16B());
+        __ Saddw(acc.V4S(), acc.V4S(), tmp.V4H());
+        __ Saddw2(acc.V4S(), acc.V4S(), tmp.V8H());
       }
       break;
     }