Quick compiler: bug fix & cleanup
Fixed a bug in bitcode generation that was helpfully masked by
gcc's -O2 optmization (code motion). Also removed quite a few fields
and identifiers left over from the JIT, along with a couple of files
that were meaningful for the JIT, but are no longer used.
Change-Id: I7702b66d646c68aafb9669368c97e128ad045dc9
diff --git a/src/compiler/CompilerIR.h b/src/compiler/CompilerIR.h
index c5bbae6..56ae486 100644
--- a/src/compiler/CompilerIR.h
+++ b/src/compiler/CompilerIR.h
@@ -34,12 +34,8 @@
#define SLOW_INVOKE_PATH (cUnit->enableDebug & (1 << kDebugSlowInvokePath))
#define SLOW_STRING_PATH (cUnit->enableDebug & (1 << kDebugSlowStringPath))
#define SLOW_TYPE_PATH (cUnit->enableDebug & (1 << kDebugSlowTypePath))
-#define EXERCISE_SLOWEST_FIELD_PATH (cUnit->enableDebug & \
- (1 << kDebugSlowestFieldPath))
#define EXERCISE_SLOWEST_STRING_PATH (cUnit->enableDebug & \
(1 << kDebugSlowestStringPath))
-#define EXERCISE_RESOLVE_METHOD (cUnit->enableDebug & \
- (1 << kDebugExerciseResolveMethod))
// Minimum field size to contain Dalvik vReg number
#define VREG_NUM_WIDTH 16
@@ -134,14 +130,11 @@
#define INVALID_SREG (-1)
#define INVALID_VREG (0xFFFFU)
#define INVALID_REG (0xFF)
-#define INVALID_OFFSET (-1)
/* SSA encodings for special registers */
#define SSA_METHOD_BASEREG (-2)
/* First compiler temp basereg, grows smaller */
#define SSA_CTEMP_BASEREG (SSA_METHOD_BASEREG - 1)
-/* Max SSA name length */
-#define SSA_NAME_MAX 16
/*
* Some code patterns cause the generation of excessively large
@@ -159,7 +152,6 @@
kDalvikByteCode,
kExitBlock,
kExceptionHandling,
- kCatchEntry,
kDead,
};
@@ -167,9 +159,6 @@
#define NEXT_LIR(lir) (lir->next)
#define PREV_LIR(lir) (lir->prev)
-#define NEXT_LIR_LVALUE(lir) (lir)->next
-#define PREV_LIR_LVALUE(lir) (lir)->prev
-
struct LIR {
int offset; // Offset of this instruction
int dalvikOffset; // Offset of Dalvik opcode
@@ -181,9 +170,8 @@
struct {
bool isNop:1; // LIR is optimized away
bool pcRelFixup:1; // May need pc-relative fixup
- unsigned int age:4; // default is 0, set lazily by the optimizer
unsigned int size:5; // in bytes
- unsigned int unused:21;
+ unsigned int unused:25;
} flags;
int aliasInfo; // For Dalvik register & litpool disambiguation
u8 useMask; // Resource mask for use
@@ -233,13 +221,6 @@
#define MIR_DUP (1 << kMIRDup)
#define MIR_MARK (1 << kMIRMark)
-struct CallsiteInfo {
- const char* classDescriptor;
- Object* classLoader;
- const Method* method;
- LIR* misPredBranchOver;
-};
-
struct Checkstats {
int nullChecks;
int nullChecksEliminated;
@@ -255,7 +236,6 @@
MIR* next;
SSARepresentation* ssaRep;
int optimizationFlags;
- int seqNum;
union {
// Used to quickly locate all Phi opcodes
MIR* phiNext;
@@ -287,9 +267,7 @@
#endif
uint16_t startOffset;
uint16_t nestingDepth;
- const Method* containingMethod; // For blocks from the callee
BBType blockType;
- bool isFallThroughFromInvoke; // True means the block needs alignment
MIR* firstMIRInsn;
MIR* lastMIRInsn;
BasicBlock* fallThrough;
@@ -325,7 +303,6 @@
enum AssemblerStatus {
kSuccess,
kRetryAll,
- kRetryHalve
};
#define NOTVISITED (-1)
@@ -347,27 +324,18 @@
literalList(NULL),
methodLiteralList(NULL),
codeLiteralList(NULL),
- classPointerList(NULL),
- numClassPointers(0),
- chainCellOffsetLIR(NULL),
disableOpt(0),
enableDebug(0),
- headerSize(0),
dataOffset(0),
totalSize(0),
assemblerStatus(kSuccess),
assemblerRetries(0),
genDebugger(false),
printMe(false),
- hasClassLiterals(false),
hasLoop(false),
hasInvoke(false),
- heapMemOp(false),
qdMode(false),
- usesLinkRegister(false),
- methodTraceSupport(false),
regPool(NULL),
- optRound(0),
instructionSet(kNone),
numSSARegs(0),
ssaBaseVRegs(NULL),
@@ -380,16 +348,13 @@
phiAliasMap(NULL),
phiList(NULL),
regLocation(NULL),
- sequenceNumber(0),
promotionMap(NULL),
methodSReg(0),
- switchOverflowPad(NULL),
numReachableBlocks(0),
numDalvikRegisters(0),
entryBlock(NULL),
exitBlock(NULL),
curBlock(NULL),
- nextCodegenBlock(NULL),
iDomList(NULL),
tryBlockAddr(NULL),
defBlockMatrix(NULL),
@@ -397,10 +362,7 @@
tempDalvikRegisterV(NULL),
tempSSARegisterV(NULL),
tempSSABlockIdV(NULL),
- printSSANames(false),
blockLabelList(NULL),
- quitLoopMode(false),
- preservedRegsUsed(0),
numIns(0),
numOuts(0),
numRegs(0),
@@ -433,7 +395,6 @@
entryBB(NULL),
entryTargetBB(NULL),
tempName(0),
- requireShadowFrame(false),
numShadowFrameEntries(0),
shadowMap(NULL),
#endif
@@ -458,12 +419,8 @@
LIR* literalList; // Constants
LIR* methodLiteralList; // Method literals requiring patching
LIR* codeLiteralList; // Code literals requiring patching
- LIR* classPointerList; // Relocatable
- int numClassPointers;
- LIR* chainCellOffsetLIR;
uint32_t disableOpt; // optControlVector flags
uint32_t enableDebug; // debugControlVector flags
- int headerSize; // bytes before the first code ptr
int dataOffset; // starting offset of literal pool
int totalSize; // header + code size
AssemblerStatus assemblerStatus; // Success or fix and retry
@@ -475,15 +432,10 @@
std::vector<uint8_t> nativeGcMap;
bool genDebugger; // Generate code for debugger
bool printMe;
- bool hasClassLiterals; // Contains class ptrs used as literals
bool hasLoop; // Contains a loop
bool hasInvoke; // Contains an invoke instruction
- bool heapMemOp; // Mark mem ops for self verification
bool qdMode; // Compile for code size/compile time
- bool usesLinkRegister; // For self-verification only
- bool methodTraceSupport; // For TraceView profiling
RegisterPool* regPool;
- int optRound; // round number to tell an LIR's age
InstructionSet instructionSet;
/* Number of total regs used in the whole cUnit after SSA transformation */
int numSSARegs;
@@ -510,7 +462,6 @@
/* Map SSA names to location */
RegLocation* regLocation;
- int sequenceNumber;
/* Keep track of Dalvik vReg to physical register mappings */
PromotionMap* promotionMap;
@@ -519,18 +470,11 @@
int methodSReg;
RegLocation methodLoc; // Describes location of method*
- /*
- * Set to the Dalvik PC of the switch instruction if it has more than
- * MAX_CHAINED_SWITCH_CASES cases.
- */
- const u2* switchOverflowPad;
-
int numReachableBlocks;
int numDalvikRegisters; // method->registersSize
BasicBlock* entryBlock;
BasicBlock* exitBlock;
BasicBlock* curBlock;
- BasicBlock* nextCodegenBlock; // for extended trace codegen
GrowableList dfsOrder;
GrowableList dfsPostOrder;
GrowableList domPostOrderTraversal;
@@ -545,10 +489,7 @@
ArenaBitVector* tempDalvikRegisterV;
ArenaBitVector* tempSSARegisterV; // numSSARegs
int* tempSSABlockIdV; // working storage for Phi labels
- bool printSSANames;
LIR* blockLabelList;
- bool quitLoopMode; // cold path/complex bytecode
- int preservedRegsUsed; // How many callee save regs used
/*
* Frame layout details.
* NOTE: for debug support it will be necessary to add a structure
@@ -612,7 +553,6 @@
SafeMap<llvm::BasicBlock*, LIR*> blockToLabelMap; // llvm bb -> LIR label
SafeMap<int32_t, llvm::BasicBlock*> idToBlockMap; // block id -> llvm bb
SafeMap<llvm::Value*, RegLocation> locMap; // llvm Value to loc rec
- bool requireShadowFrame;
int numShadowFrameEntries;
int* shadowMap;
std::set<llvm::BasicBlock*> llvmBlocks;
diff --git a/src/compiler/codegen/CodegenUtil.cc b/src/compiler/codegen/CodegenUtil.cc
index ca0a933..fa5c66f 100644
--- a/src/compiler/codegen/CodegenUtil.cc
+++ b/src/compiler/codegen/CodegenUtil.cc
@@ -421,13 +421,6 @@
for (lirInsn = cUnit->firstLIRInsn; lirInsn; lirInsn = lirInsn->next) {
oatDumpLIRInsn(cUnit, lirInsn, 0);
}
- for (lirInsn = cUnit->classPointerList; lirInsn; lirInsn = lirInsn->next) {
- thisLIR = (LIR*) lirInsn;
- LOG(INFO) << StringPrintf("%x (%04x): .class (%s)",
- thisLIR->offset, thisLIR->offset,
- ((CallsiteInfo *)
- thisLIR->operands[0])->classDescriptor);
- }
for (lirInsn = cUnit->literalList; lirInsn; lirInsn = lirInsn->next) {
thisLIR = (LIR*) lirInsn;
LOG(INFO) << StringPrintf("%x (%04x): .word (%#x)",
diff --git a/src/compiler/codegen/MethodBitcode.cc b/src/compiler/codegen/MethodBitcode.cc
index f4b8461..c50d74d 100644
--- a/src/compiler/codegen/MethodBitcode.cc
+++ b/src/compiler/codegen/MethodBitcode.cc
@@ -15,7 +15,6 @@
*/
#if defined(ART_USE_QUICK_COMPILER)
-
#include "object_utils.h"
#include <llvm/Support/ToolOutputFile.h>
@@ -1777,8 +1776,12 @@
{
if (bb->blockType == kDead) return false;
llvm::BasicBlock* llvmBB = getLLVMBlock(cUnit, bb->id);
- cUnit->irb->SetInsertPoint(llvmBB);
- setDexOffset(cUnit, bb->startOffset);
+ if (llvmBB == NULL) {
+ CHECK(bb->blockType == kExitBlock);
+ } else {
+ cUnit->irb->SetInsertPoint(llvmBB);
+ setDexOffset(cUnit, bb->startOffset);
+ }
if (cUnit->printMe) {
LOG(INFO) << "................................";
diff --git a/src/compiler/codegen/arm/armv7-a-neon/ArchVariant.cc b/src/compiler/codegen/arm/armv7-a-neon/ArchVariant.cc
deleted file mode 100644
index 0512896..0000000
--- a/src/compiler/codegen/arm/armv7-a-neon/ArchVariant.cc
+++ /dev/null
@@ -1,55 +0,0 @@
-/*
- * Copyright (C) 2011 The Android Open Source Project
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-namespace art {
-
-/*
- * Determine the initial instruction set to be used for this trace.
- * Later components may decide to change this.
- */
-InstructionSet oatInstructionSet()
-{
- return kThumb2;
-}
-
-/* Architecture-specific initializations and checks go here */
-bool oatArchVariantInit(void)
-{
- return true;
-}
-
-int oatTargetOptHint(int key)
-{
- int res = 0;
- switch (key) {
- case kMaxHoistDistance:
- res = 7;
- break;
- default:
- LOG(FATAL) << "Unknown target optimization hint key: " << key;
- }
- return res;
-}
-
-void oatGenMemBarrier(CompilationUnit* cUnit, int barrierKind)
-{
-#if ANDROID_SMP != 0
- LIR* dmb = newLIR1(cUnit, kThumb2Dmb, barrierKind);
- dmb->defMask = ENCODE_ALL;
-#endif
-}
-
-} // namespace art
diff --git a/src/compiler/codegen/arm/armv7-a-neon/Codegen.cc b/src/compiler/codegen/arm/armv7-a-neon/Codegen.cc
deleted file mode 100644
index 660d095..0000000
--- a/src/compiler/codegen/arm/armv7-a-neon/Codegen.cc
+++ /dev/null
@@ -1,58 +0,0 @@
-/*
- * Copyright (C) 2011 The Android Open Source Project
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#define _CODEGEN_C
-#define _ARMV7_A_NEON
-#define TARGET_ARM
-
-#include "../../../Dalvik.h"
-#include "../../../CompilerInternals.h"
-#include "../arm/ArmLIR.h"
-#include "../../Ralloc.h"
-#include "../Codegen.h"
-
-/* Common codegen utility code */
-#include "../../CodegenUtil.cc"
-
-/* Thumb2-specific factory utilities */
-#include "../Thumb2/Factory.cc"
-/* Target indepedent factory utilities */
-#include "../../CodegenFactory.cc"
-/* Target independent gen routines */
-#include "../../GenCommon.cc"
-/* Shared invoke gen routines */
-#include "../../GenInvoke.cc"
-/* Arm-specific factory utilities */
-#include "../ArchFactory.cc"
-
-/* Thumb2-specific codegen routines */
-#include "../Thumb2/Gen.cc"
-/* Thumb2+VFP codegen routines */
-#include "../FP/Thumb2VFP.cc"
-
-/* Thumb2-specific register allocation */
-#include "../Thumb2/Ralloc.cc"
-
-/* Bitcode conversion */
-#include "../../MethodBitcode.cc"
-
-/* MIR2LIR dispatcher and architectural independent codegen routines */
-#include "../../MethodCodegenDriver.cc"
-
-/* Target-independent local optimizations */
-#include "../../LocalOptimizations.cc"
-
-/* Architecture manifest */
-#include "ArchVariant.cc"