commit f58c11c92df59f7ec7d9f2dfadc7e400b790883d
author Douglas Leung <douglas.leung@imgtec.com> Fri Feb 13 16:53:03 2015 -0800
committer Andreas Gampe <agampe@google.com> Wed Feb 25 11:56:59 2015 -0800
tree 8d109b5ea0ca0ff07dfc589ed9542173c43d1ad9
parent 8db3d76ba7061da80f5eb58079830c796e4dea61

Fix argument register allocation for mips32.

Change-Id: Ic21b0371d7cafb9b67217b92bb2edb735a43d1b0

compiler/dex/quick/gen_invoke.cc

diff --git a/compiler/dex/quick/gen_invoke.cc b/compiler/dex/quick/gen_invoke.cc
index 040b07c..01f1d37 100755
--- a/compiler/dex/quick/gen_invoke.cc
+++ b/compiler/dex/quick/gen_invoke.cc
@@ -248,14 +248,16 @@
     if (arg0.wide == 0) {
       LoadValueDirectFixed(arg0, TargetReg(arg0.fp ? kFArg0 : kArg0, kNotWide));
       if (arg1.wide == 0) {
+        // For Mips, when the 1st arg is integral, then remaining arg are passed in core reg.
         if (cu_->instruction_set == kMips) {
-          LoadValueDirectFixed(arg1, TargetReg(arg1.fp ? kFArg2 : kArg1, kNotWide));
+          LoadValueDirectFixed(arg1, TargetReg((arg1.fp && arg0.fp) ? kFArg2 : kArg1, kNotWide));
         } else {
           LoadValueDirectFixed(arg1, TargetReg(arg1.fp ? kFArg1 : kArg1, kNotWide));
         }
       } else {
+        // For Mips, when the 1st arg is integral, then remaining arg are passed in core reg.
         if (cu_->instruction_set == kMips) {
-          LoadValueDirectWideFixed(arg1, TargetReg(arg1.fp ? kFArg2 : kArg2, kWide));
+          LoadValueDirectWideFixed(arg1, TargetReg((arg1.fp && arg0.fp) ? kFArg2 : kArg2, kWide));
         } else {
           LoadValueDirectWideFixed(arg1, TargetReg(arg1.fp ? kFArg1 : kArg1, kWide));
         }
@@ -263,9 +265,19 @@
     } else {
       LoadValueDirectWideFixed(arg0, TargetReg(arg0.fp ? kFArg0 : kArg0, kWide));
       if (arg1.wide == 0) {
-        LoadValueDirectFixed(arg1, TargetReg(arg1.fp ? kFArg2 : kArg2, kNotWide));
+        // For Mips, when the 1st arg is integral, then remaining arg are passed in core reg.
+        if (cu_->instruction_set == kMips) {
+          LoadValueDirectFixed(arg1, TargetReg((arg1.fp && arg0.fp) ? kFArg2 : kArg2, kNotWide));
+        } else {
+          LoadValueDirectFixed(arg1, TargetReg(arg1.fp ? kFArg2 : kArg2, kNotWide));
+        }
       } else {
-        LoadValueDirectWideFixed(arg1, TargetReg(arg1.fp ? kFArg2 : kArg2, kWide));
+        // For Mips, when the 1st arg is integral, then remaining arg are passed in core reg.
+        if (cu_->instruction_set == kMips) {
+          LoadValueDirectWideFixed(arg1, TargetReg((arg1.fp && arg0.fp) ? kFArg2 : kArg2, kWide));
+        } else {
+          LoadValueDirectWideFixed(arg1, TargetReg(arg1.fp ? kFArg2 : kArg2, kWide));
+        }
       }
     }
   }