ART: VIXL32: Fix assembler test after VIXL update.
Veneer pool is emitted 4 bytes later, so the expected output for
the test has been adjusted.
Test: test-art-host
Test: test-art-target
Change-Id: I3d656224fd4151904b8096486adecb6ef1eafea6
diff --git a/compiler/utils/assembler_thumb_test_expected.cc.inc b/compiler/utils/assembler_thumb_test_expected.cc.inc
index b16d99a..ab4f9e9 100644
--- a/compiler/utils/assembler_thumb_test_expected.cc.inc
+++ b/compiler/utils/assembler_thumb_test_expected.cc.inc
@@ -5537,7 +5537,7 @@
" f6: f20d 4c01 addwne ip, sp, #1025 ; 0x401\n",
" fa: f8d9 c084 ldr.w ip, [r9, #132] ; 0x84\n",
" fe: f1bc 0f00 cmp.w ip, #0\n",
- " 102: d16f bne.n 1e4 <VixlJniHelpers+0x1e4>\n",
+ " 102: d171 bne.n 1e8 <VixlJniHelpers+0x1e8>\n",
" 104: f8cd c7ff str.w ip, [sp, #2047] ; 0x7ff\n",
" 108: f8cd c7ff str.w ip, [sp, #2047] ; 0x7ff\n",
" 10c: f8cd c7ff str.w ip, [sp, #2047] ; 0x7ff\n",
@@ -5593,9 +5593,9 @@
" 1d4: f8cd c7ff str.w ip, [sp, #2047] ; 0x7ff\n",
" 1d8: f8cd c7ff str.w ip, [sp, #2047] ; 0x7ff\n",
" 1dc: f8cd c7ff str.w ip, [sp, #2047] ; 0x7ff\n",
- " 1e0: f000 b802 b.w 1e8 <VixlJniHelpers+0x1e8>\n",
- " 1e4: f000 b81a b.w 21c <VixlJniHelpers+0x21c>\n",
- " 1e8: f8cd c7ff str.w ip, [sp, #2047] ; 0x7ff\n",
+ " 1e0: f8cd c7ff str.w ip, [sp, #2047] ; 0x7ff\n",
+ " 1e4: f000 b802 b.w 1ec <VixlJniHelpers+0x1ec>\n",
+ " 1e8: f000 b818 b.w 21c <VixlJniHelpers+0x21c>\n",
" 1ec: f8cd c7ff str.w ip, [sp, #2047] ; 0x7ff\n",
" 1f0: f8cd c7ff str.w ip, [sp, #2047] ; 0x7ff\n",
" 1f4: f8cd c7ff str.w ip, [sp, #2047] ; 0x7ff\n",