Aarch64: fix bug and enable register promotion.
Iteration over arguments in invoke implementation was not correct
for wide arguments.
Change-Id: I46c7edcbfc9e32ded0e9a535fab3d333905bcf41
diff --git a/compiler/dex/frontend.cc b/compiler/dex/frontend.cc
index 8021fa4..dc6043d 100644
--- a/compiler/dex/frontend.cc
+++ b/compiler/dex/frontend.cc
@@ -869,7 +869,8 @@
} else if (cu.instruction_set == kArm64) {
// TODO(Arm64): enable optimizations once backend is mature enough.
cu.disable_opt = ~((1 << kSuppressMethodInlining) |
- (1 << kNullCheckElimination));
+ (1 << kNullCheckElimination) |
+ (1 << kPromoteRegs));
}
cu.StartTimingSplit("BuildMIRGraph");
diff --git a/compiler/dex/quick/arm64/target_arm64.cc b/compiler/dex/quick/arm64/target_arm64.cc
index 6985de6..ef9dbdd 100644
--- a/compiler/dex/quick/arm64/target_arm64.cc
+++ b/compiler/dex/quick/arm64/target_arm64.cc
@@ -1056,8 +1056,8 @@
const int last_mapped_in = in_to_reg_storage_mapping.GetMaxMappedIn();
int regs_left_to_pass_via_stack = info->num_arg_words - (last_mapped_in + 1);
- // Fisrt of all, check whether it make sense to use bulk copying
- // Optimization is aplicable only for range case
+ // First of all, check whether it makes sense to use bulk copying.
+ // Bulk copying is done only for the range case.
// TODO: make a constant instead of 2
if (info->is_range && regs_left_to_pass_via_stack >= 2) {
// Scan the rest of the args - if in phys_reg flush to memory
@@ -1141,7 +1141,6 @@
LoadValueDirectWideFixed(rl_arg, regWide);
StoreBaseDisp(TargetReg(kSp), out_offset, regWide, k64, kNotVolatile);
}
- i++;
} else {
if (rl_arg.location == kLocPhysReg) {
if (rl_arg.ref) {
@@ -1163,6 +1162,9 @@
call_state = next_call_insn(cu_, info, call_state, target_method,
vtable_idx, direct_code, direct_method, type);
}
+ if (rl_arg.wide) {
+ i++;
+ }
}
}
@@ -1174,12 +1176,14 @@
if (reg.Valid()) {
if (rl_arg.wide) {
LoadValueDirectWideFixed(rl_arg, reg);
- i++;
} else {
LoadValueDirectFixed(rl_arg, reg);
}
call_state = next_call_insn(cu_, info, call_state, target_method, vtable_idx,
- direct_code, direct_method, type);
+ direct_code, direct_method, type);
+ }
+ if (rl_arg.wide) {
+ i++;
}
}