diff --git a/compiler/optimizing/code_generator_arm_vixl.cc b/compiler/optimizing/code_generator_arm_vixl.cc
index 7f83533..7c6a5fd 100644
--- a/compiler/optimizing/code_generator_arm_vixl.cc
+++ b/compiler/optimizing/code_generator_arm_vixl.cc
@@ -5597,42 +5597,13 @@
   return Location::RequiresRegister();
 }
 
-bool LocationsBuilderARMVIXL::CanEncodeConstantAsImmediate(HConstant* input_cst,
-                                                           Opcode opcode) {
-  uint64_t value = static_cast<uint64_t>(Int64FromConstant(input_cst));
-  if (DataType::Is64BitType(input_cst->GetType())) {
-    Opcode high_opcode = opcode;
-    SetCc low_set_cc = kCcDontCare;
-    switch (opcode) {
-      case SUB:
-        // Flip the operation to an ADD.
-        value = -value;
-        opcode = ADD;
-        FALLTHROUGH_INTENDED;
-      case ADD:
-        if (Low32Bits(value) == 0u) {
-          return CanEncodeConstantAsImmediate(High32Bits(value), opcode, kCcDontCare);
-        }
-        high_opcode = ADC;
-        low_set_cc = kCcSet;
-        break;
-      default:
-        break;
-    }
-    return CanEncodeConstantAsImmediate(Low32Bits(value), opcode, low_set_cc) &&
-        CanEncodeConstantAsImmediate(High32Bits(value), high_opcode, kCcDontCare);
-  } else {
-    return CanEncodeConstantAsImmediate(Low32Bits(value), opcode);
-  }
-}
-
-// TODO(VIXL): Replace art::arm::SetCc` with `vixl32::FlagsUpdate after flags set optimization
-// enabled.
-bool LocationsBuilderARMVIXL::CanEncodeConstantAsImmediate(uint32_t value,
-                                                           Opcode opcode,
-                                                           SetCc set_cc) {
-  ArmVIXLAssembler* assembler = codegen_->GetAssembler();
-  if (assembler->ShifterOperandCanHold(opcode, value, set_cc)) {
+static bool CanEncode32BitConstantAsImmediate(
+    CodeGeneratorARMVIXL* codegen,
+    uint32_t value,
+    Opcode opcode,
+    vixl32::FlagsUpdate flags_update = vixl32::FlagsUpdate::DontCare) {
+  ArmVIXLAssembler* assembler = codegen->GetAssembler();
+  if (assembler->ShifterOperandCanHold(opcode, value, flags_update)) {
     return true;
   }
   Opcode neg_opcode = kNoOperand;
@@ -5649,13 +5620,41 @@
       return false;
   }
 
-  if (assembler->ShifterOperandCanHold(neg_opcode, neg_value, set_cc)) {
+  if (assembler->ShifterOperandCanHold(neg_opcode, neg_value, flags_update)) {
     return true;
   }
 
   return opcode == AND && IsPowerOfTwo(value + 1);
 }
 
+bool LocationsBuilderARMVIXL::CanEncodeConstantAsImmediate(HConstant* input_cst, Opcode opcode) {
+  uint64_t value = static_cast<uint64_t>(Int64FromConstant(input_cst));
+  if (DataType::Is64BitType(input_cst->GetType())) {
+    Opcode high_opcode = opcode;
+    vixl32::FlagsUpdate low_flags_update = vixl32::FlagsUpdate::DontCare;
+    switch (opcode) {
+      case SUB:
+        // Flip the operation to an ADD.
+        value = -value;
+        opcode = ADD;
+        FALLTHROUGH_INTENDED;
+      case ADD:
+        if (Low32Bits(value) == 0u) {
+          return CanEncode32BitConstantAsImmediate(codegen_, High32Bits(value), opcode);
+        }
+        high_opcode = ADC;
+        low_flags_update = vixl32::FlagsUpdate::SetFlags;
+        break;
+      default:
+        break;
+    }
+    return CanEncode32BitConstantAsImmediate(codegen_, High32Bits(value), high_opcode) &&
+           CanEncode32BitConstantAsImmediate(codegen_, Low32Bits(value), opcode, low_flags_update);
+  } else {
+    return CanEncode32BitConstantAsImmediate(codegen_, Low32Bits(value), opcode);
+  }
+}
+
 void InstructionCodeGeneratorARMVIXL::HandleFieldGet(HInstruction* instruction,
                                                      const FieldInfo& field_info) {
   DCHECK(instruction->IsInstanceFieldGet() || instruction->IsStaticFieldGet());
@@ -8131,13 +8130,11 @@
     return;
   }
   __ Adds(out_low, first_low, value_low);
-  if (GetAssembler()->ShifterOperandCanHold(ADC, value_high, kCcDontCare)) {
+  if (GetAssembler()->ShifterOperandCanHold(ADC, value_high)) {
     __ Adc(out_high, first_high, value_high);
-  } else if (GetAssembler()->ShifterOperandCanHold(SBC, ~value_high, kCcDontCare)) {
-    __ Sbc(out_high, first_high, ~value_high);
   } else {
-    LOG(FATAL) << "Unexpected constant " << value_high;
-    UNREACHABLE();
+    DCHECK(GetAssembler()->ShifterOperandCanHold(SBC, ~value_high));
+    __ Sbc(out_high, first_high, ~value_high);
   }
 }
 
diff --git a/compiler/optimizing/code_generator_arm_vixl.h b/compiler/optimizing/code_generator_arm_vixl.h
index c46d17c..38570bb 100644
--- a/compiler/optimizing/code_generator_arm_vixl.h
+++ b/compiler/optimizing/code_generator_arm_vixl.h
@@ -287,7 +287,6 @@
   Location ArithmeticZeroOrFpuRegister(HInstruction* input);
   Location ArmEncodableConstantOrRegister(HInstruction* constant, Opcode opcode);
   bool CanEncodeConstantAsImmediate(HConstant* input_cst, Opcode opcode);
-  bool CanEncodeConstantAsImmediate(uint32_t value, Opcode opcode, SetCc set_cc = kCcDontCare);
 
   CodeGeneratorARMVIXL* const codegen_;
   InvokeDexCallingConventionVisitorARMVIXL parameter_visitor_;
diff --git a/compiler/optimizing/scheduler_arm.cc b/compiler/optimizing/scheduler_arm.cc
index b3c8f10..8dcadaa 100644
--- a/compiler/optimizing/scheduler_arm.cc
+++ b/compiler/optimizing/scheduler_arm.cc
@@ -330,10 +330,12 @@
         }
       } else if (c == kCondLE || c == kCondGT) {
         if (value < std::numeric_limits<int64_t>::max() &&
-            !codegen_->GetAssembler()->ShifterOperandCanHold(SBC, High32Bits(value + 1), kCcSet)) {
+            !codegen_->GetAssembler()->ShifterOperandCanHold(
+                SBC, High32Bits(value + 1), vixl32::FlagsUpdate::SetFlags)) {
           return false;
         }
-      } else if (!codegen_->GetAssembler()->ShifterOperandCanHold(SBC, High32Bits(value), kCcSet)) {
+      } else if (!codegen_->GetAssembler()->ShifterOperandCanHold(
+                      SBC, High32Bits(value), vixl32::FlagsUpdate::SetFlags)) {
         return false;
       }
     }