Revert "Switch to LLVM prebuilt tools for ART gtests"
This reverts commit 8070443ce4b31a6787c22490f18f838f8f6ed4be.
Reason for revert: Failing on chrome buildbots.
Test: None
Bug: 137817558
Change-Id: I4cbb4898e859ce33560592dd63cbf4a413048662
diff --git a/build/makevars.go b/build/makevars.go
index 3b9d0a6..22ef205 100644
--- a/build/makevars.go
+++ b/build/makevars.go
@@ -20,21 +20,12 @@
"strings"
"android/soong/android"
+ "android/soong/cc/config"
)
var (
- pctx = android.NewPackageContext("android/soong/art")
-
- // Copy the following prebuilts to the testcases directory.
- // The original prebuilts directory is not accessible when running tests remotely.
- prebuiltToolsForTests = []string{
- "bin/clang",
- "bin/clang.real",
- "bin/llvm-addr2line",
- "bin/llvm-dwarfdump",
- "bin/llvm-objdump",
- "lib64/libc++.so.1",
- }
+ pctx = android.NewPackageContext("android/soong/art")
+ prebuiltToolsForTests = []string{"as", "addr2line", "objdump"}
)
func init() {
@@ -67,14 +58,23 @@
ctx.Strict("ART_TESTCASES_CONTENT", strings.Join(copy_cmds, " "))
// Add prebuilt tools.
- clang_path, err := ctx.Eval("${config.ClangPath}")
- if err != nil {
- panic(err)
- }
copy_cmds = []string{}
- for _, tool := range prebuiltToolsForTests {
- src := filepath.Join(clang_path, "/", tool)
- copy_cmds = append(copy_cmds, src+":"+src)
+ for _, cmd := range prebuiltToolsForTests {
+ target := ctx.Config().Targets[android.BuildOs][0]
+ toolchain := config.FindToolchain(target.Os, target.Arch)
+ gccRoot, gccTriple := toolchain.GccRoot(), toolchain.GccTriple()
+ eval := func(path ...string) string {
+ result, err := ctx.Eval(filepath.Join(path...))
+ if err != nil {
+ panic(err)
+ }
+ return result
+ }
+ src := eval(gccRoot, "bin", gccTriple+"-"+cmd)
+ // Different tests use different paths, so we need to copy to two locations.
+ // TODO: Unify the test code so that this is no longer necessary.
+ copy_cmds = append(copy_cmds, src+":"+eval(gccRoot, "bin", gccTriple+"-"+cmd))
+ copy_cmds = append(copy_cmds, src+":"+eval(gccRoot, gccTriple, "bin", cmd))
}
ctx.Strict("ART_TESTCASES_PREBUILT_CONTENT", strings.Join(copy_cmds, " "))
}
diff --git a/compiler/debug/dwarf/dwarf_test.cc b/compiler/debug/dwarf/dwarf_test.cc
index 062cfc9..95d9e93 100644
--- a/compiler/debug/dwarf/dwarf_test.cc
+++ b/compiler/debug/dwarf/dwarf_test.cc
@@ -36,87 +36,86 @@
const int offset = 40000;
ASSERT_EQ(UnsignedLeb128Size(offset / 4), 2u);
ASSERT_EQ(SignedLeb128Size(offset / 4), 3u);
+ DW_CHECK("Data alignment factor: -4");
const Reg reg(6);
// Test the opcodes in the order mentioned in the spec.
// There are usually several encoding variations of each opcode.
DebugFrameOpCodeWriter<> opcodes;
- DW_CHECK(".debug_frame contents:");
DW_CHECK("FDE");
- DW_CHECK_NEXT("DW_CFA_nop:"); // TODO: Why is a nop here.
int pc = 0;
for (int i : {0, 1, 0x3F, 0x40, 0xFF, 0x100, 0xFFFF, 0x10000}) {
pc += i;
opcodes.AdvancePC(pc);
}
- DW_CHECK_NEXT("DW_CFA_advance_loc: 1");
- DW_CHECK_NEXT("DW_CFA_advance_loc: 63");
- DW_CHECK_NEXT("DW_CFA_advance_loc1: 64");
- DW_CHECK_NEXT("DW_CFA_advance_loc1: 255");
- DW_CHECK_NEXT("DW_CFA_advance_loc2: 256");
- DW_CHECK_NEXT("DW_CFA_advance_loc2: 65535");
- DW_CHECK_NEXT("DW_CFA_advance_loc4: 65536");
+ DW_CHECK_NEXT("DW_CFA_advance_loc: 1 to 01000001");
+ DW_CHECK_NEXT("DW_CFA_advance_loc: 63 to 01000040");
+ DW_CHECK_NEXT("DW_CFA_advance_loc1: 64 to 01000080");
+ DW_CHECK_NEXT("DW_CFA_advance_loc1: 255 to 0100017f");
+ DW_CHECK_NEXT("DW_CFA_advance_loc2: 256 to 0100027f");
+ DW_CHECK_NEXT("DW_CFA_advance_loc2: 65535 to 0101027e");
+ DW_CHECK_NEXT("DW_CFA_advance_loc4: 65536 to 0102027e");
opcodes.DefCFA(reg, offset);
- DW_CHECK_NEXT("DW_CFA_def_cfa: reg6 +40000");
+ DW_CHECK_NEXT("DW_CFA_def_cfa: r6 (esi) ofs 40000");
opcodes.DefCFA(reg, -offset);
- DW_CHECK_NEXT("DW_CFA_def_cfa_sf: reg6 -40000");
+ DW_CHECK_NEXT("DW_CFA_def_cfa_sf: r6 (esi) ofs -40000");
opcodes.DefCFARegister(reg);
- DW_CHECK_NEXT("DW_CFA_def_cfa_register: reg6");
+ DW_CHECK_NEXT("DW_CFA_def_cfa_register: r6 (esi)");
opcodes.DefCFAOffset(offset);
- DW_CHECK_NEXT("DW_CFA_def_cfa_offset: +40000");
+ DW_CHECK_NEXT("DW_CFA_def_cfa_offset: 40000");
opcodes.DefCFAOffset(-offset);
DW_CHECK_NEXT("DW_CFA_def_cfa_offset_sf: -40000");
- uint8_t expr[] = { /*nop*/ 0x96 };
+ uint8_t expr[] = { 0 };
opcodes.DefCFAExpression(expr, arraysize(expr));
- DW_CHECK_NEXT("DW_CFA_def_cfa_expression: DW_OP_nop");
+ DW_CHECK_NEXT("DW_CFA_def_cfa_expression");
opcodes.Undefined(reg);
- DW_CHECK_NEXT("DW_CFA_undefined: reg6");
+ DW_CHECK_NEXT("DW_CFA_undefined: r6 (esi)");
opcodes.SameValue(reg);
- DW_CHECK_NEXT("DW_CFA_same_value: reg6");
+ DW_CHECK_NEXT("DW_CFA_same_value: r6 (esi)");
opcodes.Offset(Reg(0x3F), -offset);
- DW_CHECK_NEXT("DW_CFA_offset: reg63 -40000");
+ DW_CHECK_NEXT("DW_CFA_offset: r63 at cfa-40000");
opcodes.Offset(Reg(0x40), -offset);
- DW_CHECK_NEXT("DW_CFA_offset_extended: reg64 -40000");
+ DW_CHECK_NEXT("DW_CFA_offset_extended: r64 at cfa-40000");
opcodes.Offset(Reg(0x40), offset);
- DW_CHECK_NEXT("DW_CFA_offset_extended_sf: reg64 40000");
+ DW_CHECK_NEXT("DW_CFA_offset_extended_sf: r64 at cfa+40000");
opcodes.ValOffset(reg, -offset);
- DW_CHECK_NEXT("DW_CFA_val_offset: reg6 -40000");
+ DW_CHECK_NEXT("DW_CFA_val_offset: r6 (esi) at cfa-40000");
opcodes.ValOffset(reg, offset);
- DW_CHECK_NEXT("DW_CFA_val_offset_sf: reg6 40000");
+ DW_CHECK_NEXT("DW_CFA_val_offset_sf: r6 (esi) at cfa+40000");
opcodes.Register(reg, Reg(1));
- DW_CHECK_NEXT("DW_CFA_register: reg6 reg1");
+ DW_CHECK_NEXT("DW_CFA_register: r6 (esi) in r1 (ecx)");
opcodes.Expression(reg, expr, arraysize(expr));
- DW_CHECK_NEXT("DW_CFA_expression: reg6 DW_OP_nop");
+ DW_CHECK_NEXT("DW_CFA_expression: r6 (esi)");
opcodes.ValExpression(reg, expr, arraysize(expr));
- DW_CHECK_NEXT("DW_CFA_val_expression: reg6 DW_OP_nop");
+ DW_CHECK_NEXT("DW_CFA_val_expression: r6 (esi)");
opcodes.Restore(Reg(0x3F));
- DW_CHECK_NEXT("DW_CFA_restore: reg63");
+ DW_CHECK_NEXT("DW_CFA_restore: bad register: r63");
opcodes.Restore(Reg(0x40));
- DW_CHECK_NEXT("DW_CFA_restore_extended: reg64");
+ DW_CHECK_NEXT("DW_CFA_restore_extended: bad register: r64");
opcodes.Restore(reg);
- DW_CHECK_NEXT("DW_CFA_restore: reg6");
+ DW_CHECK_NEXT("DW_CFA_restore: r6 (esi)");
opcodes.RememberState();
- DW_CHECK_NEXT("DW_CFA_remember_state:");
+ DW_CHECK_NEXT("DW_CFA_remember_state");
opcodes.RestoreState();
- DW_CHECK_NEXT("DW_CFA_restore_state:");
+ DW_CHECK_NEXT("DW_CFA_restore_state");
opcodes.Nop();
- DW_CHECK_NEXT("DW_CFA_nop:");
+ DW_CHECK_NEXT("DW_CFA_nop");
// Also test helpers.
opcodes.DefCFA(Reg(4), 100); // ESP
- DW_CHECK_NEXT("DW_CFA_def_cfa: reg4 +100");
+ DW_CHECK_NEXT("DW_CFA_def_cfa: r4 (esp) ofs 100");
opcodes.AdjustCFAOffset(8);
- DW_CHECK_NEXT("DW_CFA_def_cfa_offset: +108");
+ DW_CHECK_NEXT("DW_CFA_def_cfa_offset: 108");
opcodes.RelOffset(Reg(0), 0); // push R0
- DW_CHECK_NEXT("DW_CFA_offset: reg0 -108");
+ DW_CHECK_NEXT("DW_CFA_offset: r0 (eax) at cfa-108");
opcodes.RelOffset(Reg(1), 4); // push R1
- DW_CHECK_NEXT("DW_CFA_offset: reg1 -104");
+ DW_CHECK_NEXT("DW_CFA_offset: r1 (ecx) at cfa-104");
opcodes.RelOffsetForMany(Reg(2), 8, 1 | (1 << 3), 4); // push R2 and R5
- DW_CHECK_NEXT("DW_CFA_offset: reg2 -100");
- DW_CHECK_NEXT("DW_CFA_offset: reg5 -96");
+ DW_CHECK_NEXT("DW_CFA_offset: r2 (edx) at cfa-100");
+ DW_CHECK_NEXT("DW_CFA_offset: r5 (ebp) at cfa-96");
opcodes.RestoreMany(Reg(2), 1 | (1 << 3)); // pop R2 and R5
- DW_CHECK_NEXT("DW_CFA_restore: reg2");
- DW_CHECK_NEXT("DW_CFA_restore: reg5");
+ DW_CHECK_NEXT("DW_CFA_restore: r2 (edx)");
+ DW_CHECK_NEXT("DW_CFA_restore: r5 (ebp)");
DebugFrameOpCodeWriter<> initial_opcodes;
WriteCIE(is64bit, Reg(is64bit ? 16 : 8), initial_opcodes, &debug_frame_data_);
@@ -127,7 +126,7 @@
ArrayRef<const uint8_t>(*opcodes.data()),
&debug_frame_data_);
- CheckObjdumpOutput(is64bit, "-debug-frame");
+ CheckObjdumpOutput(is64bit, "-W");
}
TEST_F(DwarfTest, DISABLED_DebugFrame64) {
@@ -135,7 +134,6 @@
DebugFrameOpCodeWriter<> initial_opcodes;
WriteCIE(is64bit, Reg(16), initial_opcodes, &debug_frame_data_);
DebugFrameOpCodeWriter<> opcodes;
- DW_CHECK(".debug_frame contents:");
WriteFDE(is64bit,
/* cie_pointer= */ 0,
0x0100000000000000,
@@ -144,7 +142,7 @@
&debug_frame_data_);
DW_CHECK("FDE cie=00000000 pc=100000000000000..300000000000000");
- CheckObjdumpOutput(is64bit, "-debug-frame");
+ CheckObjdumpOutput(is64bit, "-W");
}
// Test x86_64 register mapping. It is the only non-trivial architecture.
@@ -152,29 +150,26 @@
TEST_F(DwarfTest, x86_64_RegisterMapping) {
constexpr bool is64bit = true;
DebugFrameOpCodeWriter<> opcodes;
- DW_CHECK(".debug_frame contents:");
for (int i = 0; i < 16; i++) {
opcodes.RelOffset(Reg::X86_64Core(i), 0);
}
DW_CHECK("FDE");
- DW_CHECK_NEXT("DW_CFA_nop:"); // TODO: Why is a nop here.
- DW_CHECK_NEXT("DW_CFA_offset: reg0 0");
- DW_CHECK_NEXT("DW_CFA_offset: reg2 0");
- DW_CHECK_NEXT("DW_CFA_offset: reg1 0");
- DW_CHECK_NEXT("DW_CFA_offset: reg3 0");
- DW_CHECK_NEXT("DW_CFA_offset: reg7 0");
- DW_CHECK_NEXT("DW_CFA_offset: reg6 0");
- DW_CHECK_NEXT("DW_CFA_offset: reg4 0");
- DW_CHECK_NEXT("DW_CFA_offset: reg5 0");
- DW_CHECK_NEXT("DW_CFA_offset: reg8 0");
- DW_CHECK_NEXT("DW_CFA_offset: reg9 0");
- DW_CHECK_NEXT("DW_CFA_offset: reg10 0");
- DW_CHECK_NEXT("DW_CFA_offset: reg11 0");
- DW_CHECK_NEXT("DW_CFA_offset: reg12 0");
- DW_CHECK_NEXT("DW_CFA_offset: reg13 0");
- DW_CHECK_NEXT("DW_CFA_offset: reg14 0");
- DW_CHECK_NEXT("DW_CFA_offset: reg15 0");
-
+ DW_CHECK_NEXT("DW_CFA_offset: r0 (rax)");
+ DW_CHECK_NEXT("DW_CFA_offset: r2 (rcx)");
+ DW_CHECK_NEXT("DW_CFA_offset: r1 (rdx)");
+ DW_CHECK_NEXT("DW_CFA_offset: r3 (rbx)");
+ DW_CHECK_NEXT("DW_CFA_offset: r7 (rsp)");
+ DW_CHECK_NEXT("DW_CFA_offset: r6 (rbp)");
+ DW_CHECK_NEXT("DW_CFA_offset: r4 (rsi)");
+ DW_CHECK_NEXT("DW_CFA_offset: r5 (rdi)");
+ DW_CHECK_NEXT("DW_CFA_offset: r8 (r8)");
+ DW_CHECK_NEXT("DW_CFA_offset: r9 (r9)");
+ DW_CHECK_NEXT("DW_CFA_offset: r10 (r10)");
+ DW_CHECK_NEXT("DW_CFA_offset: r11 (r11)");
+ DW_CHECK_NEXT("DW_CFA_offset: r12 (r12)");
+ DW_CHECK_NEXT("DW_CFA_offset: r13 (r13)");
+ DW_CHECK_NEXT("DW_CFA_offset: r14 (r14)");
+ DW_CHECK_NEXT("DW_CFA_offset: r15 (r15)");
DebugFrameOpCodeWriter<> initial_opcodes;
WriteCIE(is64bit, Reg(16), initial_opcodes, &debug_frame_data_);
WriteFDE(is64bit,
@@ -184,67 +179,62 @@
ArrayRef<const uint8_t>(*opcodes.data()),
&debug_frame_data_);
- CheckObjdumpOutput(is64bit, "-debug-frame");
+ CheckObjdumpOutput(is64bit, "-W");
}
-TEST_F(DwarfTest, DebugLine) {
+TEST_F(DwarfTest, DISABLED_DebugLine) {
const bool is64bit = false;
const int code_factor_bits = 1;
DebugLineOpCodeWriter<> opcodes(is64bit, code_factor_bits);
- DW_CHECK(".debug_line contents:");
std::vector<std::string> include_directories;
include_directories.push_back("/path/to/source");
- DW_CHECK("include_directories[ 1] = \"/path/to/source\"");
+ DW_CHECK("/path/to/source");
std::vector<FileEntry> files {
{ "file0.c", 0, 1000, 2000 },
{ "file1.c", 1, 1000, 2000 },
{ "file2.c", 1, 1000, 2000 },
};
- DW_CHECK_NEXT("file_names[ 1]:");
- DW_CHECK_NEXT(" name: \"file0.c\"");
- DW_CHECK_NEXT(" dir_index: 0");
- DW_CHECK_NEXT(" mod_time: 0x000003e8");
- DW_CHECK_NEXT(" length: 0x000007d0");
- DW_CHECK_NEXT("file_names[ 2]:");
- DW_CHECK_NEXT(" name: \"file1.c\"");
- DW_CHECK_NEXT(" dir_index: 1");
- DW_CHECK_NEXT(" mod_time: 0x000003e8");
- DW_CHECK_NEXT(" length: 0x000007d0");
- DW_CHECK_NEXT("file_names[ 3]:");
- DW_CHECK_NEXT(" name: \"file2.c\"");
- DW_CHECK_NEXT(" dir_index: 1");
- DW_CHECK_NEXT(" mod_time: 0x000003e8");
- DW_CHECK_NEXT(" length: 0x000007d0");
- DW_CHECK_NEXT("file_names[ 4]:");
- DW_CHECK_NEXT(" name: \"file.c\"");
- DW_CHECK_NEXT(" dir_index: 0");
- DW_CHECK_NEXT(" mod_time: 0x000003e8");
- DW_CHECK_NEXT(" length: 0x000007d0");
+ DW_CHECK("1\t0\t1000\t2000\tfile0.c");
+ DW_CHECK_NEXT("2\t1\t1000\t2000\tfile1.c");
+ DW_CHECK_NEXT("3\t1\t1000\t2000\tfile2.c");
+ DW_CHECK("Line Number Statements");
opcodes.SetAddress(0x01000000);
- opcodes.SetIsStmt(true);
+ DW_CHECK_NEXT("Extended opcode 2: set Address to 0x1000000");
opcodes.AddRow();
+ DW_CHECK_NEXT("Copy");
opcodes.AdvancePC(0x01000100);
+ DW_CHECK_NEXT("Advance PC by 256 to 0x1000100");
opcodes.SetFile(2);
+ DW_CHECK_NEXT("Set File Name to entry 2 in the File Name Table");
opcodes.AdvanceLine(3);
+ DW_CHECK_NEXT("Advance Line by 2 to 3");
opcodes.SetColumn(4);
+ DW_CHECK_NEXT("Set column to 4");
+ opcodes.SetIsStmt(true);
+ DW_CHECK_NEXT("Set is_stmt to 1");
opcodes.SetIsStmt(false);
+ DW_CHECK_NEXT("Set is_stmt to 0");
opcodes.SetBasicBlock();
+ DW_CHECK_NEXT("Set basic block");
opcodes.SetPrologueEnd();
+ DW_CHECK_NEXT("Set prologue_end to true");
opcodes.SetEpilogueBegin();
+ DW_CHECK_NEXT("Set epilogue_begin to true");
opcodes.SetISA(5);
+ DW_CHECK_NEXT("Set ISA to 5");
opcodes.EndSequence();
+ DW_CHECK_NEXT("Extended opcode 1: End of Sequence");
opcodes.DefineFile("file.c", 0, 1000, 2000);
- DW_CHECK_NEXT("Address Line Column File ISA Discriminator Flags");
- DW_CHECK_NEXT("------------------ ------ ------ ------ --- ------------- -------------");
- DW_CHECK_NEXT("0x0000000001000000 1 0 1 0 0 is_stmt");
- DW_CHECK_NEXT("0x0000000001000100 3 4 2 5 0 basic_block prologue_end epilogue_begin end_sequence");
+ DW_CHECK_NEXT("Extended opcode 3: define new File Table entry");
+ DW_CHECK_NEXT("Entry\tDir\tTime\tSize\tName");
+ DW_CHECK_NEXT("1\t0\t1000\t2000\tfile.c");
WriteDebugLineTable(include_directories, files, opcodes, &debug_line_data_);
- CheckObjdumpOutput(is64bit, "-debug-line");
+ CheckObjdumpOutput(is64bit, "-W");
}
// DWARF has special one byte codes which advance PC and line at the same time.
@@ -256,11 +246,11 @@
DebugLineOpCodeWriter<> opcodes(is64bit, code_factor_bits);
opcodes.SetAddress(pc);
size_t num_rows = 0;
- DW_CHECK(".debug_line contents:");
- DW_CHECK("file_names[ 1]:");
- DW_CHECK(" name: \"file.c\"");
- DW_CHECK("Address Line Column File ISA Discriminator Flags");
- DW_CHECK("------------------ ------ ------ ------ --- ------------- -------------");
+ DW_CHECK("Line Number Statements:");
+ DW_CHECK("Special opcode");
+ DW_CHECK("Advance PC by constant");
+ DW_CHECK("Decoded dump of debug contents of section .debug_line:");
+ DW_CHECK("Line number Starting address");
for (int addr_delta = 0; addr_delta < 80; addr_delta += 2) {
for (int line_delta = 16; line_delta >= -16; --line_delta) {
pc += addr_delta;
@@ -270,74 +260,71 @@
ASSERT_EQ(opcodes.CurrentAddress(), pc);
ASSERT_EQ(opcodes.CurrentLine(), line);
char expected[1024];
- sprintf(expected, "0x%016x %6i 0 1 0 0", pc, line);
+ sprintf(expected, "%i 0x%x", line, pc);
DW_CHECK_NEXT(expected);
}
}
- opcodes.EndSequence();
EXPECT_LT(opcodes.data()->size(), num_rows * 3);
std::vector<std::string> directories;
std::vector<FileEntry> files = { { "file.c", 0, 1000, 2000 } };
WriteDebugLineTable(directories, files, opcodes, &debug_line_data_);
- CheckObjdumpOutput(is64bit, "-debug-line");
+ CheckObjdumpOutput(is64bit, "-W -WL");
}
TEST_F(DwarfTest, DebugInfo) {
constexpr bool is64bit = false;
-
DebugAbbrevWriter<> debug_abbrev(&debug_abbrev_data_);
- DW_CHECK(".debug_abbrev contents:");
- DW_CHECK_NEXT("Abbrev table for offset: 0x00000000");
- DW_CHECK_NEXT("[1] DW_TAG_compile_unit DW_CHILDREN_yes");
- DW_CHECK_NEXT(" DW_AT_producer DW_FORM_strp");
- DW_CHECK_NEXT(" DW_AT_low_pc DW_FORM_addr");
- DW_CHECK_NEXT(" DW_AT_high_pc DW_FORM_addr");
- DW_CHECK_NEXT("[2] DW_TAG_subprogram DW_CHILDREN_no");
- DW_CHECK_NEXT(" DW_AT_name DW_FORM_strp");
- DW_CHECK_NEXT(" DW_AT_low_pc DW_FORM_addr");
- DW_CHECK_NEXT(" DW_AT_high_pc DW_FORM_addr");
- DW_CHECK_NEXT("[3] DW_TAG_compile_unit DW_CHILDREN_no");
-
DebugInfoEntryWriter<> info(is64bit, &debug_abbrev);
- DW_CHECK(".debug_info contents:");
+ DW_CHECK("Contents of the .debug_info section:");
info.StartTag(dwarf::DW_TAG_compile_unit);
- DW_CHECK_NEXT("Compile Unit: length = 0x00000030 version = 0x0004 abbr_offset = 0x0000 addr_size = 0x04");
- DW_CHECK_NEXT("DW_TAG_compile_unit");
+ DW_CHECK("Abbrev Number: 1 (DW_TAG_compile_unit)");
info.WriteStrp(dwarf::DW_AT_producer, "Compiler name", &debug_str_data_);
- DW_CHECK_NEXT(" DW_AT_producer (\"Compiler name\")");
+ DW_CHECK_NEXT("DW_AT_producer : (indirect string, offset: 0x0): Compiler name");
info.WriteAddr(dwarf::DW_AT_low_pc, 0x01000000);
- DW_CHECK_NEXT(" DW_AT_low_pc (0x0000000001000000)");
+ DW_CHECK_NEXT("DW_AT_low_pc : 0x1000000");
info.WriteAddr(dwarf::DW_AT_high_pc, 0x02000000);
- DW_CHECK_NEXT(" DW_AT_high_pc (0x0000000002000000)");
+ DW_CHECK_NEXT("DW_AT_high_pc : 0x2000000");
info.StartTag(dwarf::DW_TAG_subprogram);
- DW_CHECK_NEXT(" DW_TAG_subprogram");
+ DW_CHECK("Abbrev Number: 2 (DW_TAG_subprogram)");
info.WriteStrp(dwarf::DW_AT_name, "Foo", &debug_str_data_);
- DW_CHECK_NEXT(" DW_AT_name (\"Foo\")");
+ DW_CHECK_NEXT("DW_AT_name : (indirect string, offset: 0xe): Foo");
info.WriteAddr(dwarf::DW_AT_low_pc, 0x01010000);
- DW_CHECK_NEXT(" DW_AT_low_pc (0x0000000001010000)");
+ DW_CHECK_NEXT("DW_AT_low_pc : 0x1010000");
info.WriteAddr(dwarf::DW_AT_high_pc, 0x01020000);
- DW_CHECK_NEXT(" DW_AT_high_pc (0x0000000001020000)");
+ DW_CHECK_NEXT("DW_AT_high_pc : 0x1020000");
info.EndTag(); // DW_TAG_subprogram
info.StartTag(dwarf::DW_TAG_subprogram);
- DW_CHECK_NEXT(" DW_TAG_subprogram");
+ DW_CHECK("Abbrev Number: 2 (DW_TAG_subprogram)");
info.WriteStrp(dwarf::DW_AT_name, "Bar", &debug_str_data_);
- DW_CHECK_NEXT(" DW_AT_name (\"Bar\")");
+ DW_CHECK_NEXT("DW_AT_name : (indirect string, offset: 0x12): Bar");
info.WriteAddr(dwarf::DW_AT_low_pc, 0x01020000);
- DW_CHECK_NEXT(" DW_AT_low_pc (0x0000000001020000)");
+ DW_CHECK_NEXT("DW_AT_low_pc : 0x1020000");
info.WriteAddr(dwarf::DW_AT_high_pc, 0x01030000);
- DW_CHECK_NEXT(" DW_AT_high_pc (0x0000000001030000)");
+ DW_CHECK_NEXT("DW_AT_high_pc : 0x1030000");
info.EndTag(); // DW_TAG_subprogram
info.EndTag(); // DW_TAG_compile_unit
- DW_CHECK_NEXT(" NULL");
// Test that previous list was properly terminated and empty children.
info.StartTag(dwarf::DW_TAG_compile_unit);
info.EndTag(); // DW_TAG_compile_unit
+ // The abbrev table is just side product, but check it as well.
+ DW_CHECK("Abbrev Number: 3 (DW_TAG_compile_unit)");
+ DW_CHECK("Contents of the .debug_abbrev section:");
+ DW_CHECK("1 DW_TAG_compile_unit [has children]");
+ DW_CHECK_NEXT("DW_AT_producer DW_FORM_strp");
+ DW_CHECK_NEXT("DW_AT_low_pc DW_FORM_addr");
+ DW_CHECK_NEXT("DW_AT_high_pc DW_FORM_addr");
+ DW_CHECK("2 DW_TAG_subprogram [no children]");
+ DW_CHECK_NEXT("DW_AT_name DW_FORM_strp");
+ DW_CHECK_NEXT("DW_AT_low_pc DW_FORM_addr");
+ DW_CHECK_NEXT("DW_AT_high_pc DW_FORM_addr");
+ DW_CHECK("3 DW_TAG_compile_unit [no children]");
+
dwarf::WriteDebugInfoCU(/* debug_abbrev_offset= */ 0, info, &debug_info_data_);
- CheckObjdumpOutput(is64bit, "-debug-info -debug-abbrev");
+ CheckObjdumpOutput(is64bit, "-W");
}
#endif // ART_TARGET_ANDROID
diff --git a/compiler/debug/dwarf/dwarf_test.h b/compiler/debug/dwarf/dwarf_test.h
index bad986a..caa7437 100644
--- a/compiler/debug/dwarf/dwarf_test.h
+++ b/compiler/debug/dwarf/dwarf_test.h
@@ -86,7 +86,7 @@
// Read the elf file back using objdump.
std::vector<std::string> lines;
- std::string cmd = GetAndroidTool("llvm-dwarfdump");
+ std::string cmd = GetAndroidTool("objdump");
cmd = cmd + " " + args + " " + file.GetFilename() + " 2>&1";
FILE* output = popen(cmd.data(), "r");
char buffer[1024];
@@ -96,13 +96,12 @@
printf("%s", line);
}
if (line[0] != '\0' && line[0] != '\n') {
- EXPECT_TRUE(strstr(line, "error:") == nullptr) << line;
- EXPECT_TRUE(strstr(line, "warning:") == nullptr) << line;
+ EXPECT_TRUE(strstr(line, "objdump: Error:") == nullptr) << line;
+ EXPECT_TRUE(strstr(line, "objdump: Warning:") == nullptr) << line;
std::string str(line);
if (str.back() == '\n') {
str.pop_back();
}
- std::replace(str.begin(), str.end(), '\t', ' ');
lines.push_back(str);
}
}
diff --git a/compiler/utils/assembler_test_base.h b/compiler/utils/assembler_test_base.h
index 736a292..1567367 100644
--- a/compiler/utils/assembler_test_base.h
+++ b/compiler/utils/assembler_test_base.h
@@ -135,24 +135,22 @@
}
virtual std::vector<std::string> GetAssemblerCommand() {
- InstructionSet isa = GetIsa();
- switch (isa) {
+ switch (GetIsa()) {
case InstructionSet::kX86:
- return {FindTool("clang"), "--compile", "-target", "i386-linux-gnu"};
+ return {FindTool("as"), "--32"};
case InstructionSet::kX86_64:
- return {FindTool("clang"), "--compile", "-target", "x86_64-linux-gnu"};
+ return {FindTool("as"), "--64"};
default:
- LOG(FATAL) << "Unknown instruction set: " << isa;
- UNREACHABLE();
+ return {FindTool("as")};
}
}
virtual std::vector<std::string> GetDisassemblerCommand() {
switch (GetIsa()) {
case InstructionSet::kThumb2:
- return {FindTool("llvm-objdump"), "--disassemble", "-triple", "thumbv7a-linux-gnueabi"};
+ return {FindTool("objdump"), "--disassemble", "-M", "force-thumb"};
default:
- return {FindTool("llvm-objdump"), "--disassemble", "--no-show-raw-insn"};
+ return {FindTool("objdump"), "--disassemble", "--no-show-raw-insn"};
}
}
diff --git a/compiler/utils/assembler_thumb_test.cc b/compiler/utils/assembler_thumb_test.cc
index c20100b..72dfef1 100644
--- a/compiler/utils/assembler_thumb_test.cc
+++ b/compiler/utils/assembler_thumb_test.cc
@@ -52,9 +52,9 @@
ASSERT_TRUE(Disassemble(obj_file, &disassembly));
std::string expected2 = "\n" +
- obj_file + ": file format ELF32-arm-little\n\n\n"
+ obj_file + ": file format elf32-littlearm\n\n\n"
"Disassembly of section .text:\n\n"
- "00000000 .text:\n" +
+ "00000000 <.text>:\n" +
expected;
EXPECT_EQ(expected2, disassembly);
if (expected2 != disassembly) {
diff --git a/compiler/utils/assembler_thumb_test_expected.cc.inc b/compiler/utils/assembler_thumb_test_expected.cc.inc
index b2314c5..efe62c6 100644
--- a/compiler/utils/assembler_thumb_test_expected.cc.inc
+++ b/compiler/utils/assembler_thumb_test_expected.cc.inc
@@ -1,258 +1,258 @@
const char* const VixlJniHelpersResults = {
- " 0: 2d e9 e0 4d push.w {r5, r6, r7, r8, r10, r11, lr}\n"
- " 4: 2d ed 10 8a vpush {s16, s17, s18, s19, s20, s21, s22, s23, s24, s25, s26, s27, s28, s29, s30, s31}\n"
- " 8: 89 b0 sub sp, #36\n"
- " a: 00 90 str r0, [sp]\n"
- " c: 21 91 str r1, [sp, #132]\n"
- " e: 8d ed 22 0a vstr s0, [sp, #136]\n"
- " 12: 23 92 str r2, [sp, #140]\n"
- " 14: 24 93 str r3, [sp, #144]\n"
- " 16: 88 b0 sub sp, #32\n"
- " 18: ad f5 80 5d sub.w sp, sp, #4096\n"
- " 1c: 08 98 ldr r0, [sp, #32]\n"
- " 1e: 1f 98 ldr r0, [sp, #124]\n"
- " 20: 21 98 ldr r0, [sp, #132]\n"
- " 22: ff 98 ldr r0, [sp, #1020]\n"
- " 24: dd f8 00 04 ldr.w r0, [sp, #1024]\n"
- " 28: dd f8 fc cf ldr.w r12, [sp, #4092]\n"
- " 2c: 0d f5 80 5c add.w r12, sp, #4096\n"
- " 30: dc f8 00 c0 ldr.w r12, [r12]\n"
- " 34: d9 f8 00 c2 ldr.w r12, [r9, #512]\n"
- " 38: dc f8 80 00 ldr.w r0, [r12, #128]\n"
- " 3c: 08 90 str r0, [sp, #32]\n"
- " 3e: 1f 90 str r0, [sp, #124]\n"
- " 40: 21 90 str r0, [sp, #132]\n"
- " 42: ff 90 str r0, [sp, #1020]\n"
- " 44: cd f8 00 04 str.w r0, [sp, #1024]\n"
- " 48: cd f8 fc cf str.w r12, [sp, #4092]\n"
- " 4c: 4d f8 04 5d str r5, [sp, #-4]!\n"
- " 50: 0d f5 80 55 add.w r5, sp, #4096\n"
- " 54: c5 f8 04 c0 str.w r12, [r5, #4]\n"
- " 58: 5d f8 04 5b ldr r5, [sp], #4\n"
- " 5c: 4f f0 ff 0c mov.w r12, #255\n"
- " 60: cd f8 30 c0 str.w r12, [sp, #48]\n"
- " 64: 6f f0 7f 4c mvn r12, #4278190080\n"
- " 68: cd f8 30 c0 str.w r12, [sp, #48]\n"
- " 6c: cd f8 30 c0 str.w r12, [sp, #48]\n"
- " 70: cd f8 30 c0 str.w r12, [sp, #48]\n"
- " 74: 0c 90 str r0, [sp, #48]\n"
- " 76: dd f8 30 c0 ldr.w r12, [sp, #48]\n"
- " 7a: cd f8 34 c0 str.w r12, [sp, #52]\n"
- " 7e: 0d f5 80 5c add.w r12, sp, #4096\n"
- " 82: c9 f8 00 c2 str.w r12, [r9, #512]\n"
- " 86: c9 f8 00 d2 str.w sp, [r9, #512]\n"
- " 8a: d0 f8 30 e0 ldr.w lr, [r0, #48]\n"
- " 8e: f0 47 blx lr\n"
- " 90: dd f8 2c c0 ldr.w r12, [sp, #44]\n"
- " 94: cd f8 30 c0 str.w r12, [sp, #48]\n"
- " 98: d9 f8 00 c2 ldr.w r12, [r9, #512]\n"
- " 9c: cd f8 2c c0 str.w r12, [sp, #44]\n"
- " a0: dd f8 2c c0 ldr.w r12, [sp, #44]\n"
- " a4: cd f8 30 c0 str.w r12, [sp, #48]\n"
- " a8: 48 46 mov r0, r9\n"
- " aa: cd f8 30 90 str.w r9, [sp, #48]\n"
- " ae: 04 46 mov r4, r0\n"
- " b0: bc f1 00 0f cmp.w r12, #0\n"
- " b4: 18 bf it ne\n"
- " b6: 0d f1 30 0c addne.w r12, sp, #48\n"
- " ba: 0d f1 30 0c add.w r12, sp, #48\n"
- " be: bc f1 00 0f cmp.w r12, #0\n"
- " c2: 0c bf ite eq\n"
- " c4: 00 20 moveq r0, #0\n"
- " c6: 0c a8 addne r0, sp, #48\n"
- " c8: dd f8 40 c0 ldr.w r12, [sp, #64]\n"
- " cc: bc f1 00 0f cmp.w r12, #0\n"
- " d0: 18 bf it ne\n"
- " d2: 0d f1 40 0c addne.w r12, sp, #64\n"
- " d6: cd f8 30 c0 str.w r12, [sp, #48]\n"
- " da: bc f1 00 0f cmp.w r12, #0\n"
- " de: 0c bf ite eq\n"
- " e0: 00 20 moveq r0, #0\n"
- " e2: 68 46 movne r0, sp\n"
- " e4: bc f1 00 0f cmp.w r12, #0\n"
- " e8: 0c bf ite eq\n"
- " ea: 00 20 moveq r0, #0\n"
- " ec: 0d f2 01 40 addwne r0, sp, #1025\n"
- " f0: bc f1 00 0f cmp.w r12, #0\n"
- " f4: 18 bf it ne\n"
- " f6: 0d f2 01 4c addwne r12, sp, #1025\n"
- " fa: d9 f8 a4 c0 ldr.w r12, [r9, #164]\n"
- " fe: bc f1 00 0f cmp.w r12, #0\n"
- " 102: 71 d1 bne #226\n"
- " 104: cd f8 ff c7 str.w r12, [sp, #2047]\n"
- " 108: cd f8 ff c7 str.w r12, [sp, #2047]\n"
- " 10c: cd f8 ff c7 str.w r12, [sp, #2047]\n"
- " 110: cd f8 ff c7 str.w r12, [sp, #2047]\n"
- " 114: cd f8 ff c7 str.w r12, [sp, #2047]\n"
- " 118: cd f8 ff c7 str.w r12, [sp, #2047]\n"
- " 11c: cd f8 ff c7 str.w r12, [sp, #2047]\n"
- " 120: cd f8 ff c7 str.w r12, [sp, #2047]\n"
- " 124: cd f8 ff c7 str.w r12, [sp, #2047]\n"
- " 128: cd f8 ff c7 str.w r12, [sp, #2047]\n"
- " 12c: cd f8 ff c7 str.w r12, [sp, #2047]\n"
- " 130: cd f8 ff c7 str.w r12, [sp, #2047]\n"
- " 134: cd f8 ff c7 str.w r12, [sp, #2047]\n"
- " 138: cd f8 ff c7 str.w r12, [sp, #2047]\n"
- " 13c: cd f8 ff c7 str.w r12, [sp, #2047]\n"
- " 140: cd f8 ff c7 str.w r12, [sp, #2047]\n"
- " 144: cd f8 ff c7 str.w r12, [sp, #2047]\n"
- " 148: cd f8 ff c7 str.w r12, [sp, #2047]\n"
- " 14c: cd f8 ff c7 str.w r12, [sp, #2047]\n"
- " 150: cd f8 ff c7 str.w r12, [sp, #2047]\n"
- " 154: cd f8 ff c7 str.w r12, [sp, #2047]\n"
- " 158: cd f8 ff c7 str.w r12, [sp, #2047]\n"
- " 15c: cd f8 ff c7 str.w r12, [sp, #2047]\n"
- " 160: cd f8 ff c7 str.w r12, [sp, #2047]\n"
- " 164: cd f8 ff c7 str.w r12, [sp, #2047]\n"
- " 168: cd f8 ff c7 str.w r12, [sp, #2047]\n"
- " 16c: cd f8 ff c7 str.w r12, [sp, #2047]\n"
- " 170: cd f8 ff c7 str.w r12, [sp, #2047]\n"
- " 174: cd f8 ff c7 str.w r12, [sp, #2047]\n"
- " 178: cd f8 ff c7 str.w r12, [sp, #2047]\n"
- " 17c: cd f8 ff c7 str.w r12, [sp, #2047]\n"
- " 180: cd f8 ff c7 str.w r12, [sp, #2047]\n"
- " 184: cd f8 ff c7 str.w r12, [sp, #2047]\n"
- " 188: cd f8 ff c7 str.w r12, [sp, #2047]\n"
- " 18c: cd f8 ff c7 str.w r12, [sp, #2047]\n"
- " 190: cd f8 ff c7 str.w r12, [sp, #2047]\n"
- " 194: cd f8 ff c7 str.w r12, [sp, #2047]\n"
- " 198: cd f8 ff c7 str.w r12, [sp, #2047]\n"
- " 19c: cd f8 ff c7 str.w r12, [sp, #2047]\n"
- " 1a0: cd f8 ff c7 str.w r12, [sp, #2047]\n"
- " 1a4: cd f8 ff c7 str.w r12, [sp, #2047]\n"
- " 1a8: cd f8 ff c7 str.w r12, [sp, #2047]\n"
- " 1ac: cd f8 ff c7 str.w r12, [sp, #2047]\n"
- " 1b0: cd f8 ff c7 str.w r12, [sp, #2047]\n"
- " 1b4: cd f8 ff c7 str.w r12, [sp, #2047]\n"
- " 1b8: cd f8 ff c7 str.w r12, [sp, #2047]\n"
- " 1bc: cd f8 ff c7 str.w r12, [sp, #2047]\n"
- " 1c0: cd f8 ff c7 str.w r12, [sp, #2047]\n"
- " 1c4: cd f8 ff c7 str.w r12, [sp, #2047]\n"
- " 1c8: cd f8 ff c7 str.w r12, [sp, #2047]\n"
- " 1cc: cd f8 ff c7 str.w r12, [sp, #2047]\n"
- " 1d0: cd f8 ff c7 str.w r12, [sp, #2047]\n"
- " 1d4: cd f8 ff c7 str.w r12, [sp, #2047]\n"
- " 1d8: cd f8 ff c7 str.w r12, [sp, #2047]\n"
- " 1dc: cd f8 ff c7 str.w r12, [sp, #2047]\n"
- " 1e0: cd f8 ff c7 str.w r12, [sp, #2047]\n"
- " 1e4: 00 f0 02 b8 b.w #4\n"
- " 1e8: 00 f0 1b b8 b.w #54\n"
- " 1ec: cd f8 ff c7 str.w r12, [sp, #2047]\n"
- " 1f0: cd f8 ff c7 str.w r12, [sp, #2047]\n"
- " 1f4: cd f8 ff c7 str.w r12, [sp, #2047]\n"
- " 1f8: cd f8 ff c7 str.w r12, [sp, #2047]\n"
- " 1fc: cd f8 ff c7 str.w r12, [sp, #2047]\n"
- " 200: cd f8 ff c7 str.w r12, [sp, #2047]\n"
- " 204: cd f8 ff c7 str.w r12, [sp, #2047]\n"
- " 208: cd f8 ff c7 str.w r12, [sp, #2047]\n"
- " 20c: 0d f5 80 5d add.w sp, sp, #4096\n"
- " 210: 08 b0 add sp, #32\n"
- " 212: 09 b0 add sp, #36\n"
- " 214: bd ec 10 8a vpop {s16, s17, s18, s19, s20, s21, s22, s23, s24, s25, s26, s27, s28, s29, s30, s31}\n"
- " 218: bd e8 e0 4d pop.w {r5, r6, r7, r8, r10, r11, lr}\n"
- " 21c: d9 f8 34 80 ldr.w r8, [r9, #52]\n"
- " 220: 70 47 bx lr\n"
- " 222: 60 46 mov r0, r12\n"
- " 224: d9 f8 e8 e2 ldr.w lr, [r9, #744]\n"
- " 228: f0 47 blx lr\n"
+ " 0: e92d 4de0 stmdb sp!, {r5, r6, r7, r8, sl, fp, lr}\n"
+ " 4: ed2d 8a10 vpush {s16-s31}\n"
+ " 8: b089 sub sp, #36 ; 0x24\n"
+ " a: 9000 str r0, [sp, #0]\n"
+ " c: 9121 str r1, [sp, #132] ; 0x84\n"
+ " e: ed8d 0a22 vstr s0, [sp, #136] ; 0x88\n"
+ " 12: 9223 str r2, [sp, #140] ; 0x8c\n"
+ " 14: 9324 str r3, [sp, #144] ; 0x90\n"
+ " 16: b088 sub sp, #32\n"
+ " 18: f5ad 5d80 sub.w sp, sp, #4096 ; 0x1000\n"
+ " 1c: 9808 ldr r0, [sp, #32]\n"
+ " 1e: 981f ldr r0, [sp, #124] ; 0x7c\n"
+ " 20: 9821 ldr r0, [sp, #132] ; 0x84\n"
+ " 22: 98ff ldr r0, [sp, #1020] ; 0x3fc\n"
+ " 24: f8dd 0400 ldr.w r0, [sp, #1024] ; 0x400\n"
+ " 28: f8dd cffc ldr.w ip, [sp, #4092] ; 0xffc\n"
+ " 2c: f50d 5c80 add.w ip, sp, #4096 ; 0x1000\n"
+ " 30: f8dc c000 ldr.w ip, [ip]\n"
+ " 34: f8d9 c200 ldr.w ip, [r9, #512] ; 0x200\n"
+ " 38: f8dc 0080 ldr.w r0, [ip, #128] ; 0x80\n"
+ " 3c: 9008 str r0, [sp, #32]\n"
+ " 3e: 901f str r0, [sp, #124] ; 0x7c\n"
+ " 40: 9021 str r0, [sp, #132] ; 0x84\n"
+ " 42: 90ff str r0, [sp, #1020] ; 0x3fc\n"
+ " 44: f8cd 0400 str.w r0, [sp, #1024] ; 0x400\n"
+ " 48: f8cd cffc str.w ip, [sp, #4092] ; 0xffc\n"
+ " 4c: f84d 5d04 str.w r5, [sp, #-4]!\n"
+ " 50: f50d 5580 add.w r5, sp, #4096 ; 0x1000\n"
+ " 54: f8c5 c004 str.w ip, [r5, #4]\n"
+ " 58: f85d 5b04 ldr.w r5, [sp], #4\n"
+ " 5c: f04f 0cff mov.w ip, #255 ; 0xff\n"
+ " 60: f8cd c030 str.w ip, [sp, #48] ; 0x30\n"
+ " 64: f06f 4c7f mvn.w ip, #4278190080 ; 0xff000000\n"
+ " 68: f8cd c030 str.w ip, [sp, #48] ; 0x30\n"
+ " 6c: f8cd c030 str.w ip, [sp, #48] ; 0x30\n"
+ " 70: f8cd c030 str.w ip, [sp, #48] ; 0x30\n"
+ " 74: 900c str r0, [sp, #48] ; 0x30\n"
+ " 76: f8dd c030 ldr.w ip, [sp, #48] ; 0x30\n"
+ " 7a: f8cd c034 str.w ip, [sp, #52] ; 0x34\n"
+ " 7e: f50d 5c80 add.w ip, sp, #4096 ; 0x1000\n"
+ " 82: f8c9 c200 str.w ip, [r9, #512] ; 0x200\n"
+ " 86: f8c9 d200 str.w sp, [r9, #512] ; 0x200\n"
+ " 8a: f8d0 e030 ldr.w lr, [r0, #48] ; 0x30\n"
+ " 8e: 47f0 blx lr\n"
+ " 90: f8dd c02c ldr.w ip, [sp, #44] ; 0x2c\n"
+ " 94: f8cd c030 str.w ip, [sp, #48] ; 0x30\n"
+ " 98: f8d9 c200 ldr.w ip, [r9, #512] ; 0x200\n"
+ " 9c: f8cd c02c str.w ip, [sp, #44] ; 0x2c\n"
+ " a0: f8dd c02c ldr.w ip, [sp, #44] ; 0x2c\n"
+ " a4: f8cd c030 str.w ip, [sp, #48] ; 0x30\n"
+ " a8: 4648 mov r0, r9\n"
+ " aa: f8cd 9030 str.w r9, [sp, #48] ; 0x30\n"
+ " ae: 4604 mov r4, r0\n"
+ " b0: f1bc 0f00 cmp.w ip, #0\n"
+ " b4: bf18 it ne\n"
+ " b6: f10d 0c30 addne.w ip, sp, #48 ; 0x30\n"
+ " ba: f10d 0c30 add.w ip, sp, #48 ; 0x30\n"
+ " be: f1bc 0f00 cmp.w ip, #0\n"
+ " c2: bf0c ite eq\n"
+ " c4: 2000 moveq r0, #0\n"
+ " c6: a80c addne r0, sp, #48 ; 0x30\n"
+ " c8: f8dd c040 ldr.w ip, [sp, #64] ; 0x40\n"
+ " cc: f1bc 0f00 cmp.w ip, #0\n"
+ " d0: bf18 it ne\n"
+ " d2: f10d 0c40 addne.w ip, sp, #64 ; 0x40\n"
+ " d6: f8cd c030 str.w ip, [sp, #48] ; 0x30\n"
+ " da: f1bc 0f00 cmp.w ip, #0\n"
+ " de: bf0c ite eq\n"
+ " e0: 2000 moveq r0, #0\n"
+ " e2: 4668 movne r0, sp\n"
+ " e4: f1bc 0f00 cmp.w ip, #0\n"
+ " e8: bf0c ite eq\n"
+ " ea: 2000 moveq r0, #0\n"
+ " ec: f20d 4001 addwne r0, sp, #1025 ; 0x401\n"
+ " f0: f1bc 0f00 cmp.w ip, #0\n"
+ " f4: bf18 it ne\n"
+ " f6: f20d 4c01 addwne ip, sp, #1025 ; 0x401\n"
+ " fa: f8d9 c0a4 ldr.w ip, [r9, #164] ; 0xa4\n"
+ " fe: f1bc 0f00 cmp.w ip, #0\n"
+ " 102: d171 bne.n 0x1e8\n"
+ " 104: f8cd c7ff str.w ip, [sp, #2047] ; 0x7ff\n"
+ " 108: f8cd c7ff str.w ip, [sp, #2047] ; 0x7ff\n"
+ " 10c: f8cd c7ff str.w ip, [sp, #2047] ; 0x7ff\n"
+ " 110: f8cd c7ff str.w ip, [sp, #2047] ; 0x7ff\n"
+ " 114: f8cd c7ff str.w ip, [sp, #2047] ; 0x7ff\n"
+ " 118: f8cd c7ff str.w ip, [sp, #2047] ; 0x7ff\n"
+ " 11c: f8cd c7ff str.w ip, [sp, #2047] ; 0x7ff\n"
+ " 120: f8cd c7ff str.w ip, [sp, #2047] ; 0x7ff\n"
+ " 124: f8cd c7ff str.w ip, [sp, #2047] ; 0x7ff\n"
+ " 128: f8cd c7ff str.w ip, [sp, #2047] ; 0x7ff\n"
+ " 12c: f8cd c7ff str.w ip, [sp, #2047] ; 0x7ff\n"
+ " 130: f8cd c7ff str.w ip, [sp, #2047] ; 0x7ff\n"
+ " 134: f8cd c7ff str.w ip, [sp, #2047] ; 0x7ff\n"
+ " 138: f8cd c7ff str.w ip, [sp, #2047] ; 0x7ff\n"
+ " 13c: f8cd c7ff str.w ip, [sp, #2047] ; 0x7ff\n"
+ " 140: f8cd c7ff str.w ip, [sp, #2047] ; 0x7ff\n"
+ " 144: f8cd c7ff str.w ip, [sp, #2047] ; 0x7ff\n"
+ " 148: f8cd c7ff str.w ip, [sp, #2047] ; 0x7ff\n"
+ " 14c: f8cd c7ff str.w ip, [sp, #2047] ; 0x7ff\n"
+ " 150: f8cd c7ff str.w ip, [sp, #2047] ; 0x7ff\n"
+ " 154: f8cd c7ff str.w ip, [sp, #2047] ; 0x7ff\n"
+ " 158: f8cd c7ff str.w ip, [sp, #2047] ; 0x7ff\n"
+ " 15c: f8cd c7ff str.w ip, [sp, #2047] ; 0x7ff\n"
+ " 160: f8cd c7ff str.w ip, [sp, #2047] ; 0x7ff\n"
+ " 164: f8cd c7ff str.w ip, [sp, #2047] ; 0x7ff\n"
+ " 168: f8cd c7ff str.w ip, [sp, #2047] ; 0x7ff\n"
+ " 16c: f8cd c7ff str.w ip, [sp, #2047] ; 0x7ff\n"
+ " 170: f8cd c7ff str.w ip, [sp, #2047] ; 0x7ff\n"
+ " 174: f8cd c7ff str.w ip, [sp, #2047] ; 0x7ff\n"
+ " 178: f8cd c7ff str.w ip, [sp, #2047] ; 0x7ff\n"
+ " 17c: f8cd c7ff str.w ip, [sp, #2047] ; 0x7ff\n"
+ " 180: f8cd c7ff str.w ip, [sp, #2047] ; 0x7ff\n"
+ " 184: f8cd c7ff str.w ip, [sp, #2047] ; 0x7ff\n"
+ " 188: f8cd c7ff str.w ip, [sp, #2047] ; 0x7ff\n"
+ " 18c: f8cd c7ff str.w ip, [sp, #2047] ; 0x7ff\n"
+ " 190: f8cd c7ff str.w ip, [sp, #2047] ; 0x7ff\n"
+ " 194: f8cd c7ff str.w ip, [sp, #2047] ; 0x7ff\n"
+ " 198: f8cd c7ff str.w ip, [sp, #2047] ; 0x7ff\n"
+ " 19c: f8cd c7ff str.w ip, [sp, #2047] ; 0x7ff\n"
+ " 1a0: f8cd c7ff str.w ip, [sp, #2047] ; 0x7ff\n"
+ " 1a4: f8cd c7ff str.w ip, [sp, #2047] ; 0x7ff\n"
+ " 1a8: f8cd c7ff str.w ip, [sp, #2047] ; 0x7ff\n"
+ " 1ac: f8cd c7ff str.w ip, [sp, #2047] ; 0x7ff\n"
+ " 1b0: f8cd c7ff str.w ip, [sp, #2047] ; 0x7ff\n"
+ " 1b4: f8cd c7ff str.w ip, [sp, #2047] ; 0x7ff\n"
+ " 1b8: f8cd c7ff str.w ip, [sp, #2047] ; 0x7ff\n"
+ " 1bc: f8cd c7ff str.w ip, [sp, #2047] ; 0x7ff\n"
+ " 1c0: f8cd c7ff str.w ip, [sp, #2047] ; 0x7ff\n"
+ " 1c4: f8cd c7ff str.w ip, [sp, #2047] ; 0x7ff\n"
+ " 1c8: f8cd c7ff str.w ip, [sp, #2047] ; 0x7ff\n"
+ " 1cc: f8cd c7ff str.w ip, [sp, #2047] ; 0x7ff\n"
+ " 1d0: f8cd c7ff str.w ip, [sp, #2047] ; 0x7ff\n"
+ " 1d4: f8cd c7ff str.w ip, [sp, #2047] ; 0x7ff\n"
+ " 1d8: f8cd c7ff str.w ip, [sp, #2047] ; 0x7ff\n"
+ " 1dc: f8cd c7ff str.w ip, [sp, #2047] ; 0x7ff\n"
+ " 1e0: f8cd c7ff str.w ip, [sp, #2047] ; 0x7ff\n"
+ " 1e4: f000 b802 b.w 0x1ec\n"
+ " 1e8: f000 b81b b.w 0x222\n"
+ " 1ec: f8cd c7ff str.w ip, [sp, #2047] ; 0x7ff\n"
+ " 1f0: f8cd c7ff str.w ip, [sp, #2047] ; 0x7ff\n"
+ " 1f4: f8cd c7ff str.w ip, [sp, #2047] ; 0x7ff\n"
+ " 1f8: f8cd c7ff str.w ip, [sp, #2047] ; 0x7ff\n"
+ " 1fc: f8cd c7ff str.w ip, [sp, #2047] ; 0x7ff\n"
+ " 200: f8cd c7ff str.w ip, [sp, #2047] ; 0x7ff\n"
+ " 204: f8cd c7ff str.w ip, [sp, #2047] ; 0x7ff\n"
+ " 208: f8cd c7ff str.w ip, [sp, #2047] ; 0x7ff\n"
+ " 20c: f50d 5d80 add.w sp, sp, #4096 ; 0x1000\n"
+ " 210: b008 add sp, #32\n"
+ " 212: b009 add sp, #36 ; 0x24\n"
+ " 214: ecbd 8a10 vpop {s16-s31}\n"
+ " 218: e8bd 4de0 ldmia.w sp!, {r5, r6, r7, r8, sl, fp, lr}\n"
+ " 21c: f8d9 8034 ldr.w r8, [r9, #52] ; 0x34\n"
+ " 220: 4770 bx lr\n"
+ " 222: 4660 mov r0, ip\n"
+ " 224: f8d9 e2e8 ldr.w lr, [r9, #744] ; 0x2e8\n"
+ " 228: 47f0 blx lr\n"
};
const char* const VixlLoadFromOffsetResults = {
- " 0: e2 68 ldr r2, [r4, #12]\n"
- " 2: d4 f8 ff 2f ldr.w r2, [r4, #4095]\n"
- " 6: 04 f5 80 52 add.w r2, r4, #4096\n"
- " a: 12 68 ldr r2, [r2]\n"
- " c: 04 f5 80 12 add.w r2, r4, #1048576\n"
- " 10: d2 f8 a4 20 ldr.w r2, [r2, #164]\n"
- " 14: 4f f4 80 52 mov.w r2, #4096\n"
- " 18: c0 f2 10 02 movt r2, #16\n"
- " 1c: 22 44 add r2, r4\n"
- " 1e: 12 68 ldr r2, [r2]\n"
- " 20: 4f f4 80 5c mov.w r12, #4096\n"
- " 24: c0 f2 10 0c movt r12, #16\n"
- " 28: 64 44 add r4, r12\n"
- " 2a: 24 68 ldr r4, [r4]\n"
- " 2c: a2 89 ldrh r2, [r4, #12]\n"
- " 2e: b4 f8 ff 2f ldrh.w r2, [r4, #4095]\n"
- " 32: 04 f5 80 52 add.w r2, r4, #4096\n"
- " 36: 12 88 ldrh r2, [r2]\n"
- " 38: 04 f5 80 12 add.w r2, r4, #1048576\n"
- " 3c: b2 f8 a4 20 ldrh.w r2, [r2, #164]\n"
- " 40: 4f f4 80 52 mov.w r2, #4096\n"
- " 44: c0 f2 10 02 movt r2, #16\n"
- " 48: 22 44 add r2, r4\n"
- " 4a: 12 88 ldrh r2, [r2]\n"
- " 4c: 4f f4 80 5c mov.w r12, #4096\n"
- " 50: c0 f2 10 0c movt r12, #16\n"
- " 54: 64 44 add r4, r12\n"
- " 56: 24 88 ldrh r4, [r4]\n"
- " 58: d4 e9 03 23 ldrd r2, r3, [r4, #12]\n"
- " 5c: d4 e9 ff 23 ldrd r2, r3, [r4, #1020]\n"
- " 60: 04 f5 80 62 add.w r2, r4, #1024\n"
- " 64: d2 e9 00 23 ldrd r2, r3, [r2]\n"
- " 68: 04 f5 80 22 add.w r2, r4, #262144\n"
- " 6c: d2 e9 29 23 ldrd r2, r3, [r2, #164]\n"
- " 70: 4f f4 80 62 mov.w r2, #1024\n"
- " 74: c0 f2 04 02 movt r2, #4\n"
- " 78: 22 44 add r2, r4\n"
- " 7a: d2 e9 00 23 ldrd r2, r3, [r2]\n"
- " 7e: 4f f4 80 6c mov.w r12, #1024\n"
- " 82: c0 f2 04 0c movt r12, #4\n"
- " 86: 64 44 add r4, r12\n"
- " 88: d4 e9 00 45 ldrd r4, r5, [r4]\n"
- " 8c: dc f8 0c 00 ldr.w r0, [r12, #12]\n"
- " 90: a4 f5 80 12 sub.w r2, r4, #1048576\n"
- " 94: d2 f8 a4 20 ldr.w r2, [r2, #164]\n"
- " 98: 94 f9 0c 20 ldrsb.w r2, [r4, #12]\n"
- " 9c: 22 7b ldrb r2, [r4, #12]\n"
- " 9e: b4 f9 0c 20 ldrsh.w r2, [r4, #12]\n"
+ " 0: 68e2 ldr r2, [r4, #12]\n"
+ " 2: f8d4 2fff ldr.w r2, [r4, #4095] ; 0xfff\n"
+ " 6: f504 5280 add.w r2, r4, #4096 ; 0x1000\n"
+ " a: 6812 ldr r2, [r2, #0]\n"
+ " c: f504 1280 add.w r2, r4, #1048576 ; 0x100000\n"
+ " 10: f8d2 20a4 ldr.w r2, [r2, #164] ; 0xa4\n"
+ " 14: f44f 5280 mov.w r2, #4096 ; 0x1000\n"
+ " 18: f2c0 0210 movt r2, #16\n"
+ " 1c: 4422 add r2, r4\n"
+ " 1e: 6812 ldr r2, [r2, #0]\n"
+ " 20: f44f 5c80 mov.w ip, #4096 ; 0x1000\n"
+ " 24: f2c0 0c10 movt ip, #16\n"
+ " 28: 4464 add r4, ip\n"
+ " 2a: 6824 ldr r4, [r4, #0]\n"
+ " 2c: 89a2 ldrh r2, [r4, #12]\n"
+ " 2e: f8b4 2fff ldrh.w r2, [r4, #4095] ; 0xfff\n"
+ " 32: f504 5280 add.w r2, r4, #4096 ; 0x1000\n"
+ " 36: 8812 ldrh r2, [r2, #0]\n"
+ " 38: f504 1280 add.w r2, r4, #1048576 ; 0x100000\n"
+ " 3c: f8b2 20a4 ldrh.w r2, [r2, #164] ; 0xa4\n"
+ " 40: f44f 5280 mov.w r2, #4096 ; 0x1000\n"
+ " 44: f2c0 0210 movt r2, #16\n"
+ " 48: 4422 add r2, r4\n"
+ " 4a: 8812 ldrh r2, [r2, #0]\n"
+ " 4c: f44f 5c80 mov.w ip, #4096 ; 0x1000\n"
+ " 50: f2c0 0c10 movt ip, #16\n"
+ " 54: 4464 add r4, ip\n"
+ " 56: 8824 ldrh r4, [r4, #0]\n"
+ " 58: e9d4 2303 ldrd r2, r3, [r4, #12]\n"
+ " 5c: e9d4 23ff ldrd r2, r3, [r4, #1020] ; 0x3fc\n"
+ " 60: f504 6280 add.w r2, r4, #1024 ; 0x400\n"
+ " 64: e9d2 2300 ldrd r2, r3, [r2]\n"
+ " 68: f504 2280 add.w r2, r4, #262144 ; 0x40000\n"
+ " 6c: e9d2 2329 ldrd r2, r3, [r2, #164] ; 0xa4\n"
+ " 70: f44f 6280 mov.w r2, #1024 ; 0x400\n"
+ " 74: f2c0 0204 movt r2, #4\n"
+ " 78: 4422 add r2, r4\n"
+ " 7a: e9d2 2300 ldrd r2, r3, [r2]\n"
+ " 7e: f44f 6c80 mov.w ip, #1024 ; 0x400\n"
+ " 82: f2c0 0c04 movt ip, #4\n"
+ " 86: 4464 add r4, ip\n"
+ " 88: e9d4 4500 ldrd r4, r5, [r4]\n"
+ " 8c: f8dc 000c ldr.w r0, [ip, #12]\n"
+ " 90: f5a4 1280 sub.w r2, r4, #1048576 ; 0x100000\n"
+ " 94: f8d2 20a4 ldr.w r2, [r2, #164] ; 0xa4\n"
+ " 98: f994 200c ldrsb.w r2, [r4, #12]\n"
+ " 9c: 7b22 ldrb r2, [r4, #12]\n"
+ " 9e: f9b4 200c ldrsh.w r2, [r4, #12]\n"
};
const char* const VixlStoreToOffsetResults = {
- " 0: e2 60 str r2, [r4, #12]\n"
- " 2: c4 f8 ff 2f str.w r2, [r4, #4095]\n"
- " 6: 04 f5 80 5c add.w r12, r4, #4096\n"
- " a: cc f8 00 20 str.w r2, [r12]\n"
- " e: 04 f5 80 1c add.w r12, r4, #1048576\n"
- " 12: cc f8 a4 20 str.w r2, [r12, #164]\n"
- " 16: 4f f4 80 5c mov.w r12, #4096\n"
- " 1a: c0 f2 10 0c movt r12, #16\n"
- " 1e: a4 44 add r12, r4\n"
- " 20: cc f8 00 20 str.w r2, [r12]\n"
- " 24: 4f f4 80 5c mov.w r12, #4096\n"
- " 28: c0 f2 10 0c movt r12, #16\n"
- " 2c: a4 44 add r12, r4\n"
- " 2e: cc f8 00 40 str.w r4, [r12]\n"
- " 32: a2 81 strh r2, [r4, #12]\n"
- " 34: a4 f8 ff 2f strh.w r2, [r4, #4095]\n"
- " 38: 04 f5 80 5c add.w r12, r4, #4096\n"
- " 3c: ac f8 00 20 strh.w r2, [r12]\n"
- " 40: 04 f5 80 1c add.w r12, r4, #1048576\n"
- " 44: ac f8 a4 20 strh.w r2, [r12, #164]\n"
- " 48: 4f f4 80 5c mov.w r12, #4096\n"
- " 4c: c0 f2 10 0c movt r12, #16\n"
- " 50: a4 44 add r12, r4\n"
- " 52: ac f8 00 20 strh.w r2, [r12]\n"
- " 56: 4f f4 80 5c mov.w r12, #4096\n"
- " 5a: c0 f2 10 0c movt r12, #16\n"
- " 5e: a4 44 add r12, r4\n"
- " 60: ac f8 00 40 strh.w r4, [r12]\n"
- " 64: c4 e9 03 23 strd r2, r3, [r4, #12]\n"
- " 68: c4 e9 ff 23 strd r2, r3, [r4, #1020]\n"
- " 6c: 04 f5 80 6c add.w r12, r4, #1024\n"
- " 70: cc e9 00 23 strd r2, r3, [r12]\n"
- " 74: 04 f5 80 2c add.w r12, r4, #262144\n"
- " 78: cc e9 29 23 strd r2, r3, [r12, #164]\n"
- " 7c: 4f f4 80 6c mov.w r12, #1024\n"
- " 80: c0 f2 04 0c movt r12, #4\n"
- " 84: a4 44 add r12, r4\n"
- " 86: cc e9 00 23 strd r2, r3, [r12]\n"
- " 8a: 4f f4 80 6c mov.w r12, #1024\n"
- " 8e: c0 f2 04 0c movt r12, #4\n"
- " 92: a4 44 add r12, r4\n"
- " 94: cc e9 00 45 strd r4, r5, [r12]\n"
- " 98: cc f8 0c 00 str.w r0, [r12, #12]\n"
- " 9c: a4 f5 80 1c sub.w r12, r4, #1048576\n"
- " a0: cc f8 a4 20 str.w r2, [r12, #164]\n"
- " a4: 22 73 strb r2, [r4, #12]\n"
+ " 0: 60e2 str r2, [r4, #12]\n"
+ " 2: f8c4 2fff str.w r2, [r4, #4095] ; 0xfff\n"
+ " 6: f504 5c80 add.w ip, r4, #4096 ; 0x1000\n"
+ " a: f8cc 2000 str.w r2, [ip]\n"
+ " e: f504 1c80 add.w ip, r4, #1048576 ; 0x100000\n"
+ " 12: f8cc 20a4 str.w r2, [ip, #164] ; 0xa4\n"
+ " 16: f44f 5c80 mov.w ip, #4096 ; 0x1000\n"
+ " 1a: f2c0 0c10 movt ip, #16\n"
+ " 1e: 44a4 add ip, r4\n"
+ " 20: f8cc 2000 str.w r2, [ip]\n"
+ " 24: f44f 5c80 mov.w ip, #4096 ; 0x1000\n"
+ " 28: f2c0 0c10 movt ip, #16\n"
+ " 2c: 44a4 add ip, r4\n"
+ " 2e: f8cc 4000 str.w r4, [ip]\n"
+ " 32: 81a2 strh r2, [r4, #12]\n"
+ " 34: f8a4 2fff strh.w r2, [r4, #4095] ; 0xfff\n"
+ " 38: f504 5c80 add.w ip, r4, #4096 ; 0x1000\n"
+ " 3c: f8ac 2000 strh.w r2, [ip]\n"
+ " 40: f504 1c80 add.w ip, r4, #1048576 ; 0x100000\n"
+ " 44: f8ac 20a4 strh.w r2, [ip, #164] ; 0xa4\n"
+ " 48: f44f 5c80 mov.w ip, #4096 ; 0x1000\n"
+ " 4c: f2c0 0c10 movt ip, #16\n"
+ " 50: 44a4 add ip, r4\n"
+ " 52: f8ac 2000 strh.w r2, [ip]\n"
+ " 56: f44f 5c80 mov.w ip, #4096 ; 0x1000\n"
+ " 5a: f2c0 0c10 movt ip, #16\n"
+ " 5e: 44a4 add ip, r4\n"
+ " 60: f8ac 4000 strh.w r4, [ip]\n"
+ " 64: e9c4 2303 strd r2, r3, [r4, #12]\n"
+ " 68: e9c4 23ff strd r2, r3, [r4, #1020] ; 0x3fc\n"
+ " 6c: f504 6c80 add.w ip, r4, #1024 ; 0x400\n"
+ " 70: e9cc 2300 strd r2, r3, [ip]\n"
+ " 74: f504 2c80 add.w ip, r4, #262144 ; 0x40000\n"
+ " 78: e9cc 2329 strd r2, r3, [ip, #164] ; 0xa4\n"
+ " 7c: f44f 6c80 mov.w ip, #1024 ; 0x400\n"
+ " 80: f2c0 0c04 movt ip, #4\n"
+ " 84: 44a4 add ip, r4\n"
+ " 86: e9cc 2300 strd r2, r3, [ip]\n"
+ " 8a: f44f 6c80 mov.w ip, #1024 ; 0x400\n"
+ " 8e: f2c0 0c04 movt ip, #4\n"
+ " 92: 44a4 add ip, r4\n"
+ " 94: e9cc 4500 strd r4, r5, [ip]\n"
+ " 98: f8cc 000c str.w r0, [ip, #12]\n"
+ " 9c: f5a4 1c80 sub.w ip, r4, #1048576 ; 0x100000\n"
+ " a0: f8cc 20a4 str.w r2, [ip, #164] ; 0xa4\n"
+ " a4: 7322 strb r2, [r4, #12]\n"
};
diff --git a/compiler/utils/x86_64/assembler_x86_64_test.cc b/compiler/utils/x86_64/assembler_x86_64_test.cc
index 7d196bd..30f5ef2 100644
--- a/compiler/utils/x86_64/assembler_x86_64_test.cc
+++ b/compiler/utils/x86_64/assembler_x86_64_test.cc
@@ -947,7 +947,7 @@
}
TEST_F(AssemblerX86_64Test, Xchgq) {
- DriverStr(RepeatRR(&x86_64::X86_64Assembler::xchgq, "xchgq %{reg1}, %{reg2}"), "xchgq");
+ DriverStr(RepeatRR(&x86_64::X86_64Assembler::xchgq, "xchgq %{reg2}, %{reg1}"), "xchgq");
}
TEST_F(AssemblerX86_64Test, Xchgl) {
@@ -1123,7 +1123,7 @@
}
TEST_F(AssemblerX86_64Test, Movsxd) {
- DriverStr(RepeatRr(&x86_64::X86_64Assembler::movsxd, "movslq %{reg2}, %{reg1}"), "movsxd");
+ DriverStr(RepeatRr(&x86_64::X86_64Assembler::movsxd, "movsxd %{reg2}, %{reg1}"), "movsxd");
}
TEST_F(AssemblerX86_64Test, Movaps) {
diff --git a/libartbase/base/common_art_test.cc b/libartbase/base/common_art_test.cc
index a087aa5..c6a593c 100644
--- a/libartbase/base/common_art_test.cc
+++ b/libartbase/base/common_art_test.cc
@@ -300,8 +300,24 @@
// Get prebuilt binary tool.
// The paths need to be updated when Android prebuilts update.
-std::string CommonArtTestImpl::GetAndroidTool(const char* name, InstructionSet) {
- std::string path = GetAndroidBuildTop() + "prebuilts/clang/host/linux-x86/clang-r383902b/bin/";
+std::string CommonArtTestImpl::GetAndroidTool(const char* name, InstructionSet isa) {
+ std::string path = GetAndroidBuildTop() + "prebuilts/gcc/linux-x86/";
+ switch (isa) {
+ case InstructionSet::kX86:
+ case InstructionSet::kX86_64:
+ path += "host/x86_64-linux-glibc2.17-4.8/x86_64-linux/bin/";
+ break;
+ case InstructionSet::kArm:
+ case InstructionSet::kThumb2:
+ path += "arm/arm-linux-androideabi-4.9/arm-linux-androideabi/bin/";
+ break;
+ case InstructionSet::kArm64:
+ path += "aarch64/aarch64-linux-android-4.9/aarch64-linux-android/bin/";
+ break;
+ default:
+ LOG(FATAL) << "Unknown ISA: " << isa;
+ break;
+ }
CHECK(OS::DirectoryExists(path.c_str())) << path;
path += name;
CHECK(OS::FileExists(path.c_str())) << path;
diff --git a/runtime/prebuilt_tools_test.cc b/runtime/prebuilt_tools_test.cc
index 17c0d42..15b115a 100644
--- a/runtime/prebuilt_tools_test.cc
+++ b/runtime/prebuilt_tools_test.cc
@@ -28,7 +28,7 @@
class PrebuiltToolsTest : public CommonRuntimeTest {
public:
static void CheckToolsExist(InstructionSet isa) {
- const char* tools[] = { "clang", "llvm-objdump" };
+ const char* tools[] = { "as", "objcopy", "objdump" };
for (const char* tool : tools) {
std::string path = GetAndroidTool(tool, isa);
ASSERT_TRUE(OS::FileExists(path.c_str())) << path;