commit e6ed00ba91da535fbe1d0b5a5705e99da149d82e
author Vladimir Marko <vmarko@google.com> Thu Oct 24 14:52:37 2013 +0100
committer Vladimir Marko <vmarko@google.com> Thu Oct 24 15:04:28 2013 +0100
tree a4b25369c8fa907a75a924b5def17cffd08f9fa5
parent 79b4f38dd35b83206e8166aaafb94bd75c3318b3

Fix x86 code generation for 0x0F 0x3A 0x?? instructions.

Change-Id: I9b2b2190787d1e5674818159aa96e513d6325b54

compiler/dex/quick/x86/x86_lir.h

diff --git a/compiler/dex/quick/x86/x86_lir.h b/compiler/dex/quick/x86/x86_lir.h
index 643a3d5..f1b91ca 100644
--- a/compiler/dex/quick/x86/x86_lir.h
+++ b/compiler/dex/quick/x86/x86_lir.h
@@ -243,7 +243,7 @@
   //             - lir operands - 0: base, 1: disp, 2: immediate
   // AI - Array Immediate  - opcode [base + index * scale + disp], #immediate
   //             - lir operands - 0: base, 1: index, 2: scale, 3: disp 4: immediate
-  // TI - Thread Register  - opcode fs:[disp], imm - where fs: is equal to Thread::Current()
+  // TI - Thread Immediate  - opcode fs:[disp], imm - where fs: is equal to Thread::Current()
   //             - lir operands - 0: disp, 1: imm
 #define BinaryOpCode(opcode) \
   opcode ## 8MR, opcode ## 8AR, opcode ## 8TR, \