commit e652c122d8cc9697d368b9ceada9b377d091e4fd
author xueliang.zhong <xueliang.zhong@linaro.org> Mon Jun 13 14:42:27 2016 +0100
committer Roland Levillain <rpl@google.com> Tue Jun 28 13:29:29 2016 +0000
tree 699f7f7bc88ff28d2b8f8e735ea48693aa653c95
parent ca7399a1d7b3c92d73322adf54187fde31eee1bd

ARM assembler support for VCNT and VPADDL.

Test: Gtest assembler_thumb2_test.
Change-Id: I8a0e47da746e1c67650cb68196a9f661deed7383

disassembler/disassembler_arm.cc

diff --git a/disassembler/disassembler_arm.cc b/disassembler/disassembler_arm.cc
index 286faf2..1a3e3f5 100644
--- a/disassembler/disassembler_arm.cc
+++ b/disassembler/disassembler_arm.cc
@@ -1497,6 +1497,25 @@
           }
           break;
         }
+        case 0x7B: case 0x7F: {
+          FpRegister d(instr, 12, 22);
+          FpRegister m(instr, 0, 5);
+          uint32_t sz = (instr >> 18) & 0x3;  // Decode size bits.
+          uint32_t size = (sz == 0) ? 8 : sz << 4;
+          uint32_t opc2 = (instr >> 7) & 0xF;
+          uint32_t Q = (instr >> 6) & 1;
+          if (Q == 0 && opc2 == 0xA && size == 8) {  // 1010, VCNT
+            opcode << "vcnt." << size;
+            args << d << ", " << m;
+          } else if (Q == 0 && (opc2 == 0x4 || opc2 == 0x5) && size <= 32) {  // 010x, VPADDL
+            bool op = HasBitSet(instr, 7);
+            opcode << "vpaddl." << (op ? "u" : "s") << size;
+            args << d << ", " << m;
+          } else {
+            opcode << "UNKNOWN " << op2;
+          }
+          break;
+        }
       default:      // more formats
         if ((op2 >> 4) == 2) {      // 010xxxx
           // data processing (register)