commit e36605910cb13da1440fb9d7a8293842a9209c97
author Chris Larsen <chris.larsen@imgtec.com> Wed Nov 09 11:13:42 2016 -0800
committer Chris Larsen <chris.larsen@imgtec.com> Fri Dec 02 16:22:56 2016 -0800
tree 6bb2097042a3ee4f0e0b64c4e22575823ca82c11
parent b487af4fc80ffabe0219657a9690be1316dab8e7

MIPS64: java.lang.String.getChars

Test: run-test --64 --optimizing 020-string
Test: run-test --64 020-string
Test: run-test --64 --no-prebuild --optimizing 020-string
Test: run-test --64 --no-prebuild 020-string
Test: run-test --64 --optimizing 082-inline-execute
Test: run-test --64 082-inline-execute
Test: run-test --64 --no-prebuild --optimizing 082-inline-execute
Test: run-test --64 --no-prebuild 082-inline-execute
Test: mma -j2 ART_TEST_OPTIMIZING=true test-art-target-run-test
Test: mma test-art-target-gtest -j2
Test: booted MIPS64R6 emulator.

Note: All tests run against MIPS64 QEMU.

Change-Id: I48b9a87465f2516044a2e4f598cc5dce56b0d1c9

compiler/utils/mips64/assembler_mips64.h

diff --git a/compiler/utils/mips64/assembler_mips64.h b/compiler/utils/mips64/assembler_mips64.h
index 238cb9d..7f71f96 100644
--- a/compiler/utils/mips64/assembler_mips64.h
+++ b/compiler/utils/mips64/assembler_mips64.h
@@ -393,6 +393,8 @@
   void Dshd(GpuRegister rd, GpuRegister rt);
   void Dext(GpuRegister rs, GpuRegister rt, int pos, int size);  // MIPS64
   void Dinsu(GpuRegister rt, GpuRegister rs, int pos, int size);  // MIPS64
+  void Lsa(GpuRegister rd, GpuRegister rs, GpuRegister rt, int saPlusOne);
+  void Dlsa(GpuRegister rd, GpuRegister rs, GpuRegister rt, int saPlusOne);  // MIPS64
   void Wsbh(GpuRegister rd, GpuRegister rt);
   void Sc(GpuRegister rt, GpuRegister base, int16_t imm9 = 0);
   void Scd(GpuRegister rt, GpuRegister base, int16_t imm9 = 0);