ART: Avoid shared cache lines for JIT code allocations
Dual view JIT exhibits some hygiene issues that causes crashes on
devices with 32-bit kernels.
This change makes JIT code allocations cache aligned. This is based on
guidance in the v7_coherent_user_range() that says "it is assumed that
the Icache does not read data from the write buffer".
Bug: 132205399
Test: >2000 boot tests on affected device with no zygote crashes.
Test: No crashes running ART JIT benchmarks on go/lem
Test: No failures with Treehugger
Change-Id: I901e2e5c07b9502876b33f572be63ec1dca19cbe
diff --git a/runtime/jit/jit_code_cache.h b/runtime/jit/jit_code_cache.h
index fabb978..a3e10c7 100644
--- a/runtime/jit/jit_code_cache.h
+++ b/runtime/jit/jit_code_cache.h
@@ -74,8 +74,13 @@
class MarkCodeClosure;
class ScopedCodeCacheWrite;
-// Alignment in bits that will suit all architectures.
-static constexpr int kJitCodeAlignment = 16;
+// Alignment in bytes that will suit all architectures for JIT code cache allocations. The
+// allocated block is used for method header followed by generated code. Allocations should be
+// aligned to avoid sharing cache lines between different allocations. The alignment should be
+// determined from the hardware, but this isn't readily exposed in userland plus some hardware
+// misreports.
+static constexpr int kJitCodeAlignment = 64;
+
using CodeCacheBitmap = gc::accounting::MemoryRangeBitmap<kJitCodeAlignment>;
class JitCodeCache {