Enable compiler temporaries
Compiler temporaries are a facility for having virtual register sized space
for dealing with intermediate values during MIR transformations. They receive
explicit space in managed frames so they can have a home location in case they
need to be spilled. The facility also supports "special" temporaries which
have specific semantic purpose and their location in frame must be tracked.
The compiler temporaries are treated in the same way as virtual registers
so that the MIR level transformations do not need to have special logic. However,
generated code needs to know stack layout so that it can distinguish between
home locations.
MIRGraph has received an interface for dealing with compiler temporaries. This
interface allows allocation of wide and non-wide virtual register temporaries.
The information about how temporaries are kept on stack has been moved to
stack.h. This is was necessary because stack layout is dependent on where the
temporaries are placed.
Change-Id: Iba5cf095b32feb00d3f648db112a00209c8e5f55
Signed-off-by: Razvan A Lupusoru <razvan.a.lupusoru@intel.com>
diff --git a/compiler/dex/quick/codegen_util.cc b/compiler/dex/quick/codegen_util.cc
index 7f19ea1..ec5fedd 100644
--- a/compiler/dex/quick/codegen_util.cc
+++ b/compiler/dex/quick/codegen_util.cc
@@ -252,7 +252,7 @@
}
void Mir2Lir::DumpPromotionMap() {
- int num_regs = cu_->num_dalvik_registers + cu_->num_compiler_temps + 1;
+ int num_regs = cu_->num_dalvik_registers + mir_graph_->GetNumUsedCompilerTemps();
for (int i = 0; i < num_regs; i++) {
PromotionMap v_reg_map = promotion_map_[i];
std::string buf;
@@ -289,7 +289,7 @@
LOG(INFO) << "Outs : " << cu_->num_outs;
LOG(INFO) << "CoreSpills : " << num_core_spills_;
LOG(INFO) << "FPSpills : " << num_fp_spills_;
- LOG(INFO) << "CompilerTemps : " << cu_->num_compiler_temps;
+ LOG(INFO) << "CompilerTemps : " << mir_graph_->GetNumUsedCompilerTemps();
LOG(INFO) << "Frame size : " << frame_size_;
LOG(INFO) << "code size is " << total_size_ <<
" bytes, Dalvik size is " << insns_size * 2;
@@ -1004,7 +1004,7 @@
first_lir_insn_(NULL),
last_lir_insn_(NULL) {
promotion_map_ = static_cast<PromotionMap*>
- (arena_->Alloc((cu_->num_dalvik_registers + cu_->num_compiler_temps + 1) *
+ (arena_->Alloc((cu_->num_dalvik_registers + mir_graph_->GetNumUsedCompilerTemps()) *
sizeof(promotion_map_[0]), ArenaAllocator::kAllocRegAlloc));
// Reserve pointer id 0 for NULL.
size_t null_idx = WrapPointer(NULL);
@@ -1081,13 +1081,27 @@
return result;
}
+size_t Mir2Lir::GetMaxPossibleCompilerTemps() const {
+ // Chose a reasonably small value in order to contain stack growth.
+ // Backends that are smarter about spill region can return larger values.
+ const size_t max_compiler_temps = 10;
+ return max_compiler_temps;
+}
+
+size_t Mir2Lir::GetNumBytesForCompilerTempSpillRegion() {
+ // By default assume that the Mir2Lir will need one slot for each temporary.
+ // If the backend can better determine temps that have non-overlapping ranges and
+ // temps that do not need spilled, it can actually provide a small region.
+ return (mir_graph_->GetNumUsedCompilerTemps() * sizeof(uint32_t));
+}
+
int Mir2Lir::ComputeFrameSize() {
/* Figure out the frame size */
static const uint32_t kAlignMask = kStackAlignment - 1;
- uint32_t size = (num_core_spills_ + num_fp_spills_ +
- 1 /* filler word */ + cu_->num_regs + cu_->num_outs +
- cu_->num_compiler_temps + 1 /* cur_method* */)
- * sizeof(uint32_t);
+ uint32_t size = ((num_core_spills_ + num_fp_spills_ +
+ 1 /* filler word */ + cu_->num_regs + cu_->num_outs)
+ * sizeof(uint32_t)) +
+ GetNumBytesForCompilerTempSpillRegion();
/* Align and set */
return (size + kAlignMask) & ~(kAlignMask);
}