commit d8eb2f2f2d6ddca682b4aa0703f00bb34069e298
author David Srbecky <dsrbecky@google.com> Thu Nov 29 11:11:19 2018 +0000
committer Gerrit Code Review <noreply-gerritcodereview@google.com> Thu Nov 29 11:11:19 2018 +0000
tree 1ff4cc7d77710c641e954ace980b481beb2555e8
parent 076c9da66b606057109e5fb2902d28129d120b96
parent 124bb24394ca89bdc20ff12cafc0546beaf83615

Merge "Mterp: Add missing shadow reg clear to op_long_to_double"

runtime/interpreter/mterp/arm/floating_point.S

diff --git a/runtime/interpreter/mterp/arm/floating_point.S b/runtime/interpreter/mterp/arm/floating_point.S
index 9e4d00c..035fc13 100644
--- a/runtime/interpreter/mterp/arm/floating_point.S
+++ b/runtime/interpreter/mterp/arm/floating_point.S
@@ -413,9 +413,10 @@
      */
     mov     r3, rINST, lsr #12          @ r3<- B
     ubfx    r9, rINST, #8, #4           @ r9<- A
+    CLEAR_SHADOW_PAIR r9, ip, lr        @ Zero shadow regs
     VREG_INDEX_TO_ADDR r3, r3           @ r3<- &fp[B]
     VREG_INDEX_TO_ADDR r9, r9           @ r9<- &fp[A]
-    vldr    d0, [r3]                    @ d0<- vAA
+    GET_VREG_DOUBLE_BY_ADDR d0, r3      @ d0<- vBB
     FETCH_ADVANCE_INST 1                @ advance rPC, load rINST
 
     vcvt.f64.s32    d1, s1              @ d1<- (double)(vAAh)
@@ -424,7 +425,7 @@
     vmla.f64        d2, d1, d3          @ d2<- vAAh*2^32 + vAAl
 
     GET_INST_OPCODE ip                  @ extract opcode from rINST
-    vstr.64 d2, [r9]                    @ vAA<- d2
+    SET_VREG_DOUBLE_BY_ADDR d2, r9      @ vAA<- d2
     GOTO_OPCODE ip                      @ jump to next instruction
 
     /* literal pool helper */