commit d4bccf1ece319a3a99e03ecbcbbf40bb82b9e331
author Artem Serov <artem.serov@linaro.org> Mon Apr 03 18:47:32 2017 +0100
committer Artem Serov <artem.serov@linaro.org> Mon Apr 10 11:43:33 2017 +0100
tree 2890740d9cab3eee2be223666f528c6707b89f90
parent 903b8169074c01590ab3f5ad9190d9c7e3fe795b

ARM64: Support 128-bit registers for SIMD.

Test: test-art-host, test-art-target

Change-Id: Ifb931a99d34ea77602a0e0781040ed092de9faaa

compiler/optimizing/code_generator_arm64.h

diff --git a/compiler/optimizing/code_generator_arm64.h b/compiler/optimizing/code_generator_arm64.h
index 10d8b84..869aad2 100644
--- a/compiler/optimizing/code_generator_arm64.h
+++ b/compiler/optimizing/code_generator_arm64.h
@@ -412,8 +412,9 @@
   }
 
   size_t GetFloatingPointSpillSlotSize() const OVERRIDE {
-    // Allocated in D registers, which are word sized.
-    return kArm64WordSize;
+    return GetGraph()->HasSIMD()
+        ? 2 * kArm64WordSize   // 16 bytes == 2 arm64 words for each spill
+        : 1 * kArm64WordSize;  //  8 bytes == 1 arm64 words for each spill
   }
 
   uintptr_t GetAddressOf(HBasicBlock* block) OVERRIDE {