ART: Refactor SIMD slots and regs size processing.
ART vectorizer assumes that there is single size of SIMD
register used for the whole program. Make this assumption explicit
and refactor the code.
Note: This is a base for the future introduction of SIMD slots of
size other than 8 or 16 bytes.
Test: test-art-target, test-art-host.
Change-Id: Id699d5e3590ca8c655ecd9f9ed4e63f49e3c4f9c
diff --git a/compiler/optimizing/loop_optimization.h b/compiler/optimizing/loop_optimization.h
index 1a842c4..0c35f29 100644
--- a/compiler/optimizing/loop_optimization.h
+++ b/compiler/optimizing/loop_optimization.h
@@ -38,7 +38,7 @@
class HLoopOptimization : public HOptimization {
public:
HLoopOptimization(HGraph* graph,
- const CompilerOptions* compiler_options,
+ const CodeGenerator& codegen, // Needs info about the target.
HInductionVarAnalysis* induction_analysis,
OptimizingCompilerStats* stats,
const char* name = kLoopOptimizationPassName);
@@ -186,7 +186,15 @@
uint64_t restrictions);
uint32_t GetVectorSizeInBytes();
bool TrySetVectorType(DataType::Type type, /*out*/ uint64_t* restrictions);
- bool TrySetVectorLength(uint32_t length);
+ bool TrySetVectorLengthImpl(uint32_t length);
+
+ bool TrySetVectorLength(DataType::Type type, uint32_t length) {
+ bool res = TrySetVectorLengthImpl(length);
+ // Currently the vectorizer supports only the mode when full SIMD registers are used.
+ DCHECK(!res || (DataType::Size(type) * length == GetVectorSizeInBytes()));
+ return res;
+ }
+
void GenerateVecInv(HInstruction* org, DataType::Type type);
void GenerateVecSub(HInstruction* org, HInstruction* offset);
void GenerateVecMem(HInstruction* org,
@@ -265,6 +273,9 @@
// Compiler options (to query ISA features).
const CompilerOptions* compiler_options_;
+ // Cached target SIMD vector register size in bytes.
+ const size_t simd_register_size_;
+
// Range information based on prior induction variable analysis.
InductionVarRange induction_range_;