ART: Refactor SIMD slots and regs size processing.
ART vectorizer assumes that there is single size of SIMD
register used for the whole program. Make this assumption explicit
and refactor the code.
Note: This is a base for the future introduction of SIMD slots of
size other than 8 or 16 bytes.
Test: test-art-target, test-art-host.
Change-Id: Id699d5e3590ca8c655ecd9f9ed4e63f49e3c4f9c
diff --git a/compiler/optimizing/code_generator_arm_vixl.h b/compiler/optimizing/code_generator_arm_vixl.h
index 48fb082..3eed730 100644
--- a/compiler/optimizing/code_generator_arm_vixl.h
+++ b/compiler/optimizing/code_generator_arm_vixl.h
@@ -450,6 +450,13 @@
return vixl::aarch32::kSRegSizeInBytes;
}
+ size_t GetSIMDRegisterWidth() const override {
+ // ARM 32-bit backend doesn't support Q registers in vectorizer, only D
+ // registers (due to register allocator restrictions: overlapping s/d/q
+ // registers).
+ return vixl::aarch32::kDRegSizeInBytes;
+ }
+
HGraphVisitor* GetLocationBuilder() override { return &location_builder_; }
HGraphVisitor* GetInstructionVisitor() override { return &instruction_visitor_; }