commit c8150b5def82058c23df377a5006a78e7668afeb
author Artem Serov <artem.serov@linaro.org> Wed Jul 31 18:28:00 2019 +0100
committer Treehugger Robot <treehugger-gerrit@google.com> Fri Apr 17 10:35:45 2020 +0000
tree 8f0e15b91cd55b978ca7f152206f0a550353810a
parent b2028739a2db03623ed76f5028ede1333c48f4c9

ART: Refactor SIMD slots and regs size processing.

ART vectorizer assumes that there is single size of SIMD
register used for the whole program. Make this assumption explicit
and refactor the code.

Note: This is a base for the future introduction of SIMD slots of
size other than 8 or 16 bytes.

Test: test-art-target, test-art-host.
Change-Id: Id699d5e3590ca8c655ecd9f9ed4e63f49e3c4f9c

compiler/optimizing/code_generator_arm64.h

diff --git a/compiler/optimizing/code_generator_arm64.h b/compiler/optimizing/code_generator_arm64.h
index 6b2c805..47a0194 100644
--- a/compiler/optimizing/code_generator_arm64.h
+++ b/compiler/optimizing/code_generator_arm64.h
@@ -437,7 +437,7 @@
 
   size_t GetSlowPathFPWidth() const override {
     return GetGraph()->HasSIMD()
-        ? vixl::aarch64::kQRegSizeInBytes
+        ? GetSIMDRegisterWidth()
         : vixl::aarch64::kDRegSizeInBytes;
   }
 
@@ -445,6 +445,10 @@
     return vixl::aarch64::kDRegSizeInBytes;
   }
 
+  size_t GetSIMDRegisterWidth() const override {
+    return vixl::aarch64::kQRegSizeInBytes;
+  }
+
   uintptr_t GetAddressOf(HBasicBlock* block) override {
     vixl::aarch64::Label* block_entry_label = GetLabelOf(block);
     DCHECK(block_entry_label->IsBound());