Introduce support for hardware simulators, starting with ARM64

Simulator support for ARM64 is implemented with VIXL.
Now codegen_test will also run on all supported hardware simulators.

Change-Id: Idc740f566175d1a23c373ea9292b8fc5ba526d00
diff --git a/compiler/optimizing/codegen_test.cc b/compiler/optimizing/codegen_test.cc
index 4fbb51d..715eca4 100644
--- a/compiler/optimizing/codegen_test.cc
+++ b/compiler/optimizing/codegen_test.cc
@@ -40,6 +40,7 @@
 #include "optimizing_unit_test.h"
 #include "prepare_for_register_allocation.h"
 #include "register_allocator.h"
+#include "simulator/code_simulator.h"
 #include "ssa_liveness_analysis.h"
 #include "utils.h"
 #include "utils/arm/managed_register_arm.h"
@@ -120,26 +121,78 @@
   DISALLOW_COPY_AND_ASSIGN(InternalCodeAllocator);
 };
 
+static bool CanExecute(InstructionSet target_isa) {
+  return (target_isa == kRuntimeISA) || CodeSimulator::CanSimulate(target_isa);
+}
+
+template <typename Expected>
+static Expected SimulatorExecute(CodeSimulator* simulator, Expected (*f)());
+
+template <>
+bool SimulatorExecute<bool>(CodeSimulator* simulator, bool (*f)()) {
+  simulator->RunFrom(reinterpret_cast<intptr_t>(f));
+  return simulator->GetCReturnBool();
+}
+
+template <>
+int32_t SimulatorExecute<int32_t>(CodeSimulator* simulator, int32_t (*f)()) {
+  simulator->RunFrom(reinterpret_cast<intptr_t>(f));
+  return simulator->GetCReturnInt32();
+}
+
+template <>
+int64_t SimulatorExecute<int64_t>(CodeSimulator* simulator, int64_t (*f)()) {
+  simulator->RunFrom(reinterpret_cast<intptr_t>(f));
+  return simulator->GetCReturnInt64();
+}
+
+template <typename Expected>
+static void VerifyGeneratedCode(InstructionSet target_isa,
+                                Expected (*f)(),
+                                bool has_result,
+                                Expected expected) {
+  ASSERT_TRUE(CanExecute(target_isa)) << "Target isa is not executable.";
+
+  // Verify on simulator.
+  if (CodeSimulator::CanSimulate(target_isa)) {
+    std::unique_ptr<CodeSimulator> simulator(CodeSimulator::CreateCodeSimulator(target_isa));
+    Expected result = SimulatorExecute<Expected>(simulator.get(), f);
+    if (has_result) {
+      ASSERT_EQ(expected, result);
+    }
+  }
+
+  // Verify on hardware.
+  if (kRuntimeISA == target_isa) {
+    Expected result = f();
+    if (has_result) {
+      ASSERT_EQ(expected, result);
+    }
+  }
+}
+
 template <typename Expected>
 static void Run(const InternalCodeAllocator& allocator,
                 const CodeGenerator& codegen,
                 bool has_result,
                 Expected expected) {
+  InstructionSet target_isa = codegen.GetInstructionSet();
+
   typedef Expected (*fptr)();
   CommonCompilerTest::MakeExecutable(allocator.GetMemory(), allocator.GetSize());
   fptr f = reinterpret_cast<fptr>(allocator.GetMemory());
-  if (codegen.GetInstructionSet() == kThumb2) {
+  if (target_isa == kThumb2) {
     // For thumb we need the bottom bit set.
     f = reinterpret_cast<fptr>(reinterpret_cast<uintptr_t>(f) + 1);
   }
-  Expected result = f();
-  if (has_result) {
-    ASSERT_EQ(expected, result);
-  }
+  VerifyGeneratedCode(target_isa, f, has_result, expected);
 }
 
 template <typename Expected>
-static void RunCodeBaseline(HGraph* graph, bool has_result, Expected expected) {
+static void RunCodeBaseline(InstructionSet target_isa,
+                            HGraph* graph,
+                            bool has_result,
+                            Expected expected) {
   InternalCodeAllocator allocator;
 
   CompilerOptions compiler_options;
@@ -149,7 +202,7 @@
   // We avoid doing a stack overflow check that requires the runtime being setup,
   // by making sure the compiler knows the methods we are running are leaf methods.
   codegenX86.CompileBaseline(&allocator, true);
-  if (kRuntimeISA == kX86) {
+  if (target_isa == kX86) {
     Run(allocator, codegenX86, has_result, expected);
   }
 
@@ -157,7 +210,7 @@
       ArmInstructionSetFeatures::FromCppDefines());
   TestCodeGeneratorARM codegenARM(graph, *features_arm.get(), compiler_options);
   codegenARM.CompileBaseline(&allocator, true);
-  if (kRuntimeISA == kArm || kRuntimeISA == kThumb2) {
+  if (target_isa == kArm || target_isa == kThumb2) {
     Run(allocator, codegenARM, has_result, expected);
   }
 
@@ -165,7 +218,7 @@
       X86_64InstructionSetFeatures::FromCppDefines());
   x86_64::CodeGeneratorX86_64 codegenX86_64(graph, *features_x86_64.get(), compiler_options);
   codegenX86_64.CompileBaseline(&allocator, true);
-  if (kRuntimeISA == kX86_64) {
+  if (target_isa == kX86_64) {
     Run(allocator, codegenX86_64, has_result, expected);
   }
 
@@ -173,7 +226,7 @@
       Arm64InstructionSetFeatures::FromCppDefines());
   arm64::CodeGeneratorARM64 codegenARM64(graph, *features_arm64.get(), compiler_options);
   codegenARM64.CompileBaseline(&allocator, true);
-  if (kRuntimeISA == kArm64) {
+  if (target_isa == kArm64) {
     Run(allocator, codegenARM64, has_result, expected);
   }
 
@@ -181,7 +234,7 @@
       Mips64InstructionSetFeatures::FromCppDefines());
   mips64::CodeGeneratorMIPS64 codegenMIPS64(graph, *features_mips64.get(), compiler_options);
   codegenMIPS64.CompileBaseline(&allocator, true);
-  if (kRuntimeISA == kMips64) {
+  if (target_isa == kMips64) {
     Run(allocator, codegenMIPS64, has_result, expected);
   }
 }
@@ -209,32 +262,33 @@
 }
 
 template <typename Expected>
-static void RunCodeOptimized(HGraph* graph,
+static void RunCodeOptimized(InstructionSet target_isa,
+                             HGraph* graph,
                              std::function<void(HGraph*)> hook_before_codegen,
                              bool has_result,
                              Expected expected) {
   CompilerOptions compiler_options;
-  if (kRuntimeISA == kArm || kRuntimeISA == kThumb2) {
-    TestCodeGeneratorARM codegenARM(graph,
-                                    *ArmInstructionSetFeatures::FromCppDefines(),
-                                    compiler_options);
+  if (target_isa == kArm || target_isa == kThumb2) {
+    std::unique_ptr<const ArmInstructionSetFeatures> features_arm(
+        ArmInstructionSetFeatures::FromCppDefines());
+    TestCodeGeneratorARM codegenARM(graph, *features_arm.get(), compiler_options);
     RunCodeOptimized(&codegenARM, graph, hook_before_codegen, has_result, expected);
-  } else if (kRuntimeISA == kArm64) {
-    arm64::CodeGeneratorARM64 codegenARM64(graph,
-                                           *Arm64InstructionSetFeatures::FromCppDefines(),
-                                           compiler_options);
+  } else if (target_isa == kArm64) {
+    std::unique_ptr<const Arm64InstructionSetFeatures> features_arm64(
+        Arm64InstructionSetFeatures::FromCppDefines());
+    arm64::CodeGeneratorARM64 codegenARM64(graph, *features_arm64.get(), compiler_options);
     RunCodeOptimized(&codegenARM64, graph, hook_before_codegen, has_result, expected);
-  } else if (kRuntimeISA == kX86) {
+  } else if (target_isa == kX86) {
     std::unique_ptr<const X86InstructionSetFeatures> features_x86(
         X86InstructionSetFeatures::FromCppDefines());
     x86::CodeGeneratorX86 codegenX86(graph, *features_x86.get(), compiler_options);
     RunCodeOptimized(&codegenX86, graph, hook_before_codegen, has_result, expected);
-  } else if (kRuntimeISA == kX86_64) {
+  } else if (target_isa == kX86_64) {
     std::unique_ptr<const X86_64InstructionSetFeatures> features_x86_64(
         X86_64InstructionSetFeatures::FromCppDefines());
     x86_64::CodeGeneratorX86_64 codegenX86_64(graph, *features_x86_64.get(), compiler_options);
     RunCodeOptimized(&codegenX86_64, graph, hook_before_codegen, has_result, expected);
-  } else if (kRuntimeISA == kMips64) {
+  } else if (target_isa == kMips64) {
     std::unique_ptr<const Mips64InstructionSetFeatures> features_mips64(
         Mips64InstructionSetFeatures::FromCppDefines());
     mips64::CodeGeneratorMIPS64 codegenMIPS64(graph, *features_mips64.get(), compiler_options);
@@ -242,7 +296,10 @@
   }
 }
 
-static void TestCode(const uint16_t* data, bool has_result = false, int32_t expected = 0) {
+static void TestCode(InstructionSet target_isa,
+                     const uint16_t* data,
+                     bool has_result = false,
+                     int32_t expected = 0) {
   ArenaPool pool;
   ArenaAllocator arena(&pool);
   HGraph* graph = CreateGraph(&arena);
@@ -252,10 +309,13 @@
   ASSERT_TRUE(graph_built);
   // Remove suspend checks, they cannot be executed in this context.
   RemoveSuspendChecks(graph);
-  RunCodeBaseline(graph, has_result, expected);
+  RunCodeBaseline(target_isa, graph, has_result, expected);
 }
 
-static void TestCodeLong(const uint16_t* data, bool has_result, int64_t expected) {
+static void TestCodeLong(InstructionSet target_isa,
+                         const uint16_t* data,
+                         bool has_result,
+                         int64_t expected) {
   ArenaPool pool;
   ArenaAllocator arena(&pool);
   HGraph* graph = CreateGraph(&arena);
@@ -265,108 +325,110 @@
   ASSERT_TRUE(graph_built);
   // Remove suspend checks, they cannot be executed in this context.
   RemoveSuspendChecks(graph);
-  RunCodeBaseline(graph, has_result, expected);
+  RunCodeBaseline(target_isa, graph, has_result, expected);
 }
 
-TEST(CodegenTest, ReturnVoid) {
+class CodegenTest: public ::testing::TestWithParam<InstructionSet> {};
+
+TEST_P(CodegenTest, ReturnVoid) {
   const uint16_t data[] = ZERO_REGISTER_CODE_ITEM(Instruction::RETURN_VOID);
-  TestCode(data);
+  TestCode(GetParam(), data);
 }
 
-TEST(CodegenTest, CFG1) {
+TEST_P(CodegenTest, CFG1) {
   const uint16_t data[] = ZERO_REGISTER_CODE_ITEM(
     Instruction::GOTO | 0x100,
     Instruction::RETURN_VOID);
 
-  TestCode(data);
+  TestCode(GetParam(), data);
 }
 
-TEST(CodegenTest, CFG2) {
+TEST_P(CodegenTest, CFG2) {
   const uint16_t data[] = ZERO_REGISTER_CODE_ITEM(
     Instruction::GOTO | 0x100,
     Instruction::GOTO | 0x100,
     Instruction::RETURN_VOID);
 
-  TestCode(data);
+  TestCode(GetParam(), data);
 }
 
-TEST(CodegenTest, CFG3) {
+TEST_P(CodegenTest, CFG3) {
   const uint16_t data1[] = ZERO_REGISTER_CODE_ITEM(
     Instruction::GOTO | 0x200,
     Instruction::RETURN_VOID,
     Instruction::GOTO | 0xFF00);
 
-  TestCode(data1);
+  TestCode(GetParam(), data1);
 
   const uint16_t data2[] = ZERO_REGISTER_CODE_ITEM(
     Instruction::GOTO_16, 3,
     Instruction::RETURN_VOID,
     Instruction::GOTO_16, 0xFFFF);
 
-  TestCode(data2);
+  TestCode(GetParam(), data2);
 
   const uint16_t data3[] = ZERO_REGISTER_CODE_ITEM(
     Instruction::GOTO_32, 4, 0,
     Instruction::RETURN_VOID,
     Instruction::GOTO_32, 0xFFFF, 0xFFFF);
 
-  TestCode(data3);
+  TestCode(GetParam(), data3);
 }
 
-TEST(CodegenTest, CFG4) {
+TEST_P(CodegenTest, CFG4) {
   const uint16_t data[] = ZERO_REGISTER_CODE_ITEM(
     Instruction::RETURN_VOID,
     Instruction::GOTO | 0x100,
     Instruction::GOTO | 0xFE00);
 
-  TestCode(data);
+  TestCode(GetParam(), data);
 }
 
-TEST(CodegenTest, CFG5) {
+TEST_P(CodegenTest, CFG5) {
   const uint16_t data[] = ONE_REGISTER_CODE_ITEM(
     Instruction::CONST_4 | 0 | 0,
     Instruction::IF_EQ, 3,
     Instruction::GOTO | 0x100,
     Instruction::RETURN_VOID);
 
-  TestCode(data);
+  TestCode(GetParam(), data);
 }
 
-TEST(CodegenTest, IntConstant) {
+TEST_P(CodegenTest, IntConstant) {
   const uint16_t data[] = ONE_REGISTER_CODE_ITEM(
     Instruction::CONST_4 | 0 | 0,
     Instruction::RETURN_VOID);
 
-  TestCode(data);
+  TestCode(GetParam(), data);
 }
 
-TEST(CodegenTest, Return1) {
+TEST_P(CodegenTest, Return1) {
   const uint16_t data[] = ONE_REGISTER_CODE_ITEM(
     Instruction::CONST_4 | 0 | 0,
     Instruction::RETURN | 0);
 
-  TestCode(data, true, 0);
+  TestCode(GetParam(), data, true, 0);
 }
 
-TEST(CodegenTest, Return2) {
+TEST_P(CodegenTest, Return2) {
   const uint16_t data[] = TWO_REGISTERS_CODE_ITEM(
     Instruction::CONST_4 | 0 | 0,
     Instruction::CONST_4 | 0 | 1 << 8,
     Instruction::RETURN | 1 << 8);
 
-  TestCode(data, true, 0);
+  TestCode(GetParam(), data, true, 0);
 }
 
-TEST(CodegenTest, Return3) {
+TEST_P(CodegenTest, Return3) {
   const uint16_t data[] = TWO_REGISTERS_CODE_ITEM(
     Instruction::CONST_4 | 0 | 0,
     Instruction::CONST_4 | 1 << 8 | 1 << 12,
     Instruction::RETURN | 1 << 8);
 
-  TestCode(data, true, 1);
+  TestCode(GetParam(), data, true, 1);
 }
 
-TEST(CodegenTest, ReturnIf1) {
+TEST_P(CodegenTest, ReturnIf1) {
   const uint16_t data[] = TWO_REGISTERS_CODE_ITEM(
     Instruction::CONST_4 | 0 | 0,
     Instruction::CONST_4 | 1 << 8 | 1 << 12,
@@ -374,10 +436,10 @@
     Instruction::RETURN | 0 << 8,
     Instruction::RETURN | 1 << 8);
 
-  TestCode(data, true, 1);
+  TestCode(GetParam(), data, true, 1);
 }
 
-TEST(CodegenTest, ReturnIf2) {
+TEST_P(CodegenTest, ReturnIf2) {
   const uint16_t data[] = TWO_REGISTERS_CODE_ITEM(
     Instruction::CONST_4 | 0 | 0,
     Instruction::CONST_4 | 1 << 8 | 1 << 12,
@@ -385,12 +447,12 @@
     Instruction::RETURN | 0 << 8,
     Instruction::RETURN | 1 << 8);
 
-  TestCode(data, true, 0);
+  TestCode(GetParam(), data, true, 0);
 }
 
 // Exercise bit-wise (one's complement) not-int instruction.
 #define NOT_INT_TEST(TEST_NAME, INPUT, EXPECTED_OUTPUT) \
-TEST(CodegenTest, TEST_NAME) {                          \
+TEST_P(CodegenTest, TEST_NAME) {                        \
   const int32_t input = INPUT;                          \
   const uint16_t input_lo = Low16Bits(input);           \
   const uint16_t input_hi = High16Bits(input);          \
@@ -399,7 +461,7 @@
       Instruction::NOT_INT | 1 << 8 | 0 << 12 ,         \
       Instruction::RETURN | 1 << 8);                    \
                                                         \
-  TestCode(data, true, EXPECTED_OUTPUT);                \
+  TestCode(GetParam(), data, true, EXPECTED_OUTPUT);    \
 }
 
 NOT_INT_TEST(ReturnNotIntMinus2, -2, 1)
@@ -415,7 +477,7 @@
 
 // Exercise bit-wise (one's complement) not-long instruction.
 #define NOT_LONG_TEST(TEST_NAME, INPUT, EXPECTED_OUTPUT)                 \
-TEST(CodegenTest, TEST_NAME) {                                           \
+TEST_P(CodegenTest, TEST_NAME) {                                         \
   const int64_t input = INPUT;                                           \
   const uint16_t word0 = Low16Bits(Low32Bits(input));   /* LSW. */       \
   const uint16_t word1 = High16Bits(Low32Bits(input));                   \
@@ -426,7 +488,7 @@
       Instruction::NOT_LONG | 2 << 8 | 0 << 12,                          \
       Instruction::RETURN_WIDE | 2 << 8);                                \
                                                                          \
-  TestCodeLong(data, true, EXPECTED_OUTPUT);                             \
+  TestCodeLong(GetParam(), data, true, EXPECTED_OUTPUT);                 \
 }
 
 NOT_LONG_TEST(ReturnNotLongMinus2, INT64_C(-2), INT64_C(1))
@@ -465,7 +527,7 @@
 
 #undef NOT_LONG_TEST
 
-TEST(CodegenTest, IntToLongOfLongToInt) {
+TEST_P(CodegenTest, IntToLongOfLongToInt) {
   const int64_t input = INT64_C(4294967296);             // 2^32
   const uint16_t word0 = Low16Bits(Low32Bits(input));    // LSW.
   const uint16_t word1 = High16Bits(Low32Bits(input));
@@ -479,48 +541,48 @@
       Instruction::INT_TO_LONG | 2 << 8 | 4 << 12,
       Instruction::RETURN_WIDE | 2 << 8);
 
-  TestCodeLong(data, true, 1);
+  TestCodeLong(GetParam(), data, true, 1);
 }
 
-TEST(CodegenTest, ReturnAdd1) {
+TEST_P(CodegenTest, ReturnAdd1) {
   const uint16_t data[] = TWO_REGISTERS_CODE_ITEM(
     Instruction::CONST_4 | 3 << 12 | 0,
     Instruction::CONST_4 | 4 << 12 | 1 << 8,
     Instruction::ADD_INT, 1 << 8 | 0,
     Instruction::RETURN);
 
-  TestCode(data, true, 7);
+  TestCode(GetParam(), data, true, 7);
 }
 
-TEST(CodegenTest, ReturnAdd2) {
+TEST_P(CodegenTest, ReturnAdd2) {
   const uint16_t data[] = TWO_REGISTERS_CODE_ITEM(
     Instruction::CONST_4 | 3 << 12 | 0,
     Instruction::CONST_4 | 4 << 12 | 1 << 8,
     Instruction::ADD_INT_2ADDR | 1 << 12,
     Instruction::RETURN);
 
-  TestCode(data, true, 7);
+  TestCode(GetParam(), data, true, 7);
 }
 
-TEST(CodegenTest, ReturnAdd3) {
+TEST_P(CodegenTest, ReturnAdd3) {
   const uint16_t data[] = ONE_REGISTER_CODE_ITEM(
     Instruction::CONST_4 | 4 << 12 | 0 << 8,
     Instruction::ADD_INT_LIT8, 3 << 8 | 0,
     Instruction::RETURN);
 
-  TestCode(data, true, 7);
+  TestCode(GetParam(), data, true, 7);
 }
 
-TEST(CodegenTest, ReturnAdd4) {
+TEST_P(CodegenTest, ReturnAdd4) {
   const uint16_t data[] = ONE_REGISTER_CODE_ITEM(
     Instruction::CONST_4 | 4 << 12 | 0 << 8,
     Instruction::ADD_INT_LIT16, 3,
     Instruction::RETURN);
 
-  TestCode(data, true, 7);
+  TestCode(GetParam(), data, true, 7);
 }
 
-TEST(CodegenTest, NonMaterializedCondition) {
+TEST_P(CodegenTest, NonMaterializedCondition) {
   ArenaPool pool;
   ArenaAllocator allocator(&pool);
 
@@ -566,30 +628,30 @@
     block->InsertInstructionBefore(move, block->GetLastInstruction());
   };
 
-  RunCodeOptimized(graph, hook_before_codegen, true, 0);
+  RunCodeOptimized(GetParam(), graph, hook_before_codegen, true, 0);
 }
 
-TEST(CodegenTest, ReturnMulInt) {
+TEST_P(CodegenTest, ReturnMulInt) {
   const uint16_t data[] = TWO_REGISTERS_CODE_ITEM(
     Instruction::CONST_4 | 3 << 12 | 0,
     Instruction::CONST_4 | 4 << 12 | 1 << 8,
     Instruction::MUL_INT, 1 << 8 | 0,
     Instruction::RETURN);
 
-  TestCode(data, true, 12);
+  TestCode(GetParam(), data, true, 12);
 }
 
-TEST(CodegenTest, ReturnMulInt2addr) {
+TEST_P(CodegenTest, ReturnMulInt2addr) {
   const uint16_t data[] = TWO_REGISTERS_CODE_ITEM(
     Instruction::CONST_4 | 3 << 12 | 0,
     Instruction::CONST_4 | 4 << 12 | 1 << 8,
     Instruction::MUL_INT_2ADDR | 1 << 12,
     Instruction::RETURN);
 
-  TestCode(data, true, 12);
+  TestCode(GetParam(), data, true, 12);
 }
 
-TEST(CodegenTest, ReturnMulLong) {
+TEST_P(CodegenTest, ReturnMulLong) {
   const uint16_t data[] = FOUR_REGISTERS_CODE_ITEM(
     Instruction::CONST_4 | 3 << 12 | 0,
     Instruction::CONST_4 | 0 << 12 | 1 << 8,
@@ -598,10 +660,10 @@
     Instruction::MUL_LONG, 2 << 8 | 0,
     Instruction::RETURN_WIDE);
 
-  TestCodeLong(data, true, 12);
+  TestCodeLong(GetParam(), data, true, 12);
 }
 
-TEST(CodegenTest, ReturnMulLong2addr) {
+TEST_P(CodegenTest, ReturnMulLong2addr) {
   const uint16_t data[] = FOUR_REGISTERS_CODE_ITEM(
     Instruction::CONST_4 | 3 << 12 | 0 << 8,
     Instruction::CONST_4 | 0 << 12 | 1 << 8,
@@ -610,28 +672,28 @@
     Instruction::MUL_LONG_2ADDR | 2 << 12,
     Instruction::RETURN_WIDE);
 
-  TestCodeLong(data, true, 12);
+  TestCodeLong(GetParam(), data, true, 12);
 }
 
-TEST(CodegenTest, ReturnMulIntLit8) {
+TEST_P(CodegenTest, ReturnMulIntLit8) {
   const uint16_t data[] = ONE_REGISTER_CODE_ITEM(
     Instruction::CONST_4 | 4 << 12 | 0 << 8,
     Instruction::MUL_INT_LIT8, 3 << 8 | 0,
     Instruction::RETURN);
 
-  TestCode(data, true, 12);
+  TestCode(GetParam(), data, true, 12);
 }
 
-TEST(CodegenTest, ReturnMulIntLit16) {
+TEST_P(CodegenTest, ReturnMulIntLit16) {
   const uint16_t data[] = ONE_REGISTER_CODE_ITEM(
     Instruction::CONST_4 | 4 << 12 | 0 << 8,
     Instruction::MUL_INT_LIT16, 3,
     Instruction::RETURN);
 
-  TestCode(data, true, 12);
+  TestCode(GetParam(), data, true, 12);
 }
 
-TEST(CodegenTest, MaterializedCondition1) {
+TEST_P(CodegenTest, MaterializedCondition1) {
   // Check that condition are materialized correctly. A materialized condition
   // should yield `1` if it evaluated to true, and `0` otherwise.
   // We force the materialization of comparisons for different combinations of
@@ -672,11 +734,11 @@
       block->InsertInstructionBefore(move, block->GetLastInstruction());
     };
 
-    RunCodeOptimized(graph, hook_before_codegen, true, lhs[i] < rhs[i]);
+    RunCodeOptimized(GetParam(), graph, hook_before_codegen, true, lhs[i] < rhs[i]);
   }
 }
 
-TEST(CodegenTest, MaterializedCondition2) {
+TEST_P(CodegenTest, MaterializedCondition2) {
   // Check that HIf correctly interprets a materialized condition.
   // We force the materialization of comparisons for different combinations of
   // inputs. An HIf takes the materialized combination as input and returns a
@@ -738,27 +800,53 @@
       block->InsertInstructionBefore(move, block->GetLastInstruction());
     };
 
-    RunCodeOptimized(graph, hook_before_codegen, true, lhs[i] < rhs[i]);
+    RunCodeOptimized(GetParam(), graph, hook_before_codegen, true, lhs[i] < rhs[i]);
   }
 }
 
-TEST(CodegenTest, ReturnDivIntLit8) {
+TEST_P(CodegenTest, ReturnDivIntLit8) {
   const uint16_t data[] = ONE_REGISTER_CODE_ITEM(
     Instruction::CONST_4 | 4 << 12 | 0 << 8,
     Instruction::DIV_INT_LIT8, 3 << 8 | 0,
     Instruction::RETURN);
 
-  TestCode(data, true, 1);
+  TestCode(GetParam(), data, true, 1);
 }
 
-TEST(CodegenTest, ReturnDivInt2Addr) {
+TEST_P(CodegenTest, ReturnDivInt2Addr) {
   const uint16_t data[] = TWO_REGISTERS_CODE_ITEM(
     Instruction::CONST_4 | 4 << 12 | 0,
     Instruction::CONST_4 | 2 << 12 | 1 << 8,
     Instruction::DIV_INT_2ADDR | 1 << 12,
     Instruction::RETURN);
 
-  TestCode(data, true, 2);
+  TestCode(GetParam(), data, true, 2);
 }
 
+static ::std::vector<InstructionSet> GetTargetISAs() {
+  ::std::vector<InstructionSet> v;
+  // Add all ISAs that are executable on hardware or on simulator.
+  const ::std::vector<InstructionSet> executable_isa_candidates = {
+    kArm,
+    kArm64,
+    kThumb2,
+    kX86,
+    kX86_64,
+    kMips,
+    kMips64
+  };
+
+  for (auto target_isa : executable_isa_candidates) {
+    if (CanExecute(target_isa)) {
+      v.push_back(target_isa);
+    }
+  }
+
+  return v;
+}
+
+INSTANTIATE_TEST_CASE_P(MultipleTargets,
+                        CodegenTest,
+                        ::testing::ValuesIn(GetTargetISAs()));
+
 }  // namespace art
diff --git a/runtime/Android.mk b/runtime/Android.mk
index 8f70d30..254c08c 100644
--- a/runtime/Android.mk
+++ b/runtime/Android.mk
@@ -196,6 +196,8 @@
   arch/x86/instruction_set_features_x86.cc \
   arch/x86/registers_x86.cc \
   arch/x86_64/registers_x86_64.cc \
+  simulator/code_simulator.cc \
+  simulator/code_simulator_arm64.cc \
   entrypoints/entrypoint_utils.cc \
   entrypoints/interpreter/interpreter_entrypoints.cc \
   entrypoints/jni/jni_entrypoints.cc \
@@ -494,11 +496,11 @@
     LOCAL_SHARED_LIBRARIES += libcutils
   else # host
     ifeq ($$(art_static_or_shared),static)
-      LOCAL_STATIC_LIBRARIES += libziparchive-host libz
+      LOCAL_STATIC_LIBRARIES += libziparchive-host libz libvixl
       # For ashmem_create_region.
       LOCAL_STATIC_LIBRARIES += libcutils
     else
-      LOCAL_SHARED_LIBRARIES += libziparchive-host libz-host
+      LOCAL_SHARED_LIBRARIES += libziparchive-host libz-host libvixl
       # For ashmem_create_region.
       LOCAL_SHARED_LIBRARIES += libcutils
     endif
diff --git a/runtime/simulator/code_simulator.cc b/runtime/simulator/code_simulator.cc
new file mode 100644
index 0000000..5023e48
--- /dev/null
+++ b/runtime/simulator/code_simulator.cc
@@ -0,0 +1,42 @@
+/*
+ * Copyright (C) 2015 The Android Open Source Project
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "simulator/code_simulator.h"
+#include "simulator/code_simulator_arm64.h"
+
+namespace art {
+
+CodeSimulator* CodeSimulator::CreateCodeSimulator(InstructionSet target_isa) {
+  DCHECK(CanSimulate(target_isa));
+  switch (target_isa) {
+    case kArm64:
+      return new arm64::CodeSimulatorArm64();
+    default:
+      UNREACHABLE();
+  }
+}
+
+bool CodeSimulator::CanSimulate(InstructionSet target_isa) {
+  switch (target_isa) {
+    case kArm64:
+      return arm64::CodeSimulatorArm64::CanSimulateArm64();
+    default:
+      // No simulator support for target.
+      return false;
+  }
+}
+
+}  // namespace art
diff --git a/runtime/simulator/code_simulator.h b/runtime/simulator/code_simulator.h
new file mode 100644
index 0000000..fe24c95
--- /dev/null
+++ b/runtime/simulator/code_simulator.h
@@ -0,0 +1,40 @@
+/*
+ * Copyright (C) 2015 The Android Open Source Project
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef ART_RUNTIME_SIMULATOR_CODE_SIMULATOR_H_
+#define ART_RUNTIME_SIMULATOR_CODE_SIMULATOR_H_
+
+#include "arch/instruction_set.h"
+
+namespace art {
+
+class CodeSimulator {
+ public:
+  virtual ~CodeSimulator() {}
+  static CodeSimulator* CreateCodeSimulator(InstructionSet target_isa);
+  static bool CanSimulate(InstructionSet target_isa);
+
+  virtual void RunFrom(intptr_t code_buffer) = 0;
+
+  // Get return value according to C ABI.
+  virtual bool GetCReturnBool() = 0;
+  virtual int32_t GetCReturnInt32() = 0;
+  virtual int64_t GetCReturnInt64() = 0;
+};
+
+}  // namespace art
+
+#endif  // ART_RUNTIME_SIMULATOR_CODE_SIMULATOR_H_
diff --git a/runtime/simulator/code_simulator_arm64.cc b/runtime/simulator/code_simulator_arm64.cc
new file mode 100644
index 0000000..3472e80
--- /dev/null
+++ b/runtime/simulator/code_simulator_arm64.cc
@@ -0,0 +1,68 @@
+/*
+ * Copyright (C) 2015 The Android Open Source Project
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "simulator/code_simulator_arm64.h"
+
+namespace art {
+namespace arm64 {
+
+// VIXL has not been tested on 32bit arches, so vixl::Simulator is not always
+// available. To avoid linker error on these arches, an early return is added in
+// each of the following methods, when vixl::Simulator is not available.
+// TODO: when vixl::Simulator is always available, remove the early returns.
+
+CodeSimulatorArm64::CodeSimulatorArm64()
+    : decoder_(nullptr), simulator_(nullptr) {
+  DCHECK(kCanSimulate);
+  if (!kCanSimulate) {
+    return;
+  }
+  decoder_ = new vixl::Decoder();
+  simulator_ = new vixl::Simulator(decoder_);
+}
+
+CodeSimulatorArm64::~CodeSimulatorArm64() {
+  if (!kCanSimulate) {
+    return;
+  }
+  delete simulator_;
+  delete decoder_;
+}
+
+void CodeSimulatorArm64::RunFrom(intptr_t code_buffer) {
+  if (!kCanSimulate) {
+    return;
+  }
+  simulator_->RunFrom(reinterpret_cast<const vixl::Instruction*>(code_buffer));
+}
+
+bool CodeSimulatorArm64::GetCReturnBool() {
+  DCHECK(kCanSimulate);
+  return simulator_->wreg(0);
+}
+
+int32_t CodeSimulatorArm64::GetCReturnInt32() {
+  DCHECK(kCanSimulate);
+  return simulator_->wreg(0);
+}
+
+int64_t CodeSimulatorArm64::GetCReturnInt64() {
+  DCHECK(kCanSimulate);
+  return simulator_->xreg(0);
+}
+
+}  // namespace arm64
+}  // namespace art
diff --git a/runtime/simulator/code_simulator_arm64.h b/runtime/simulator/code_simulator_arm64.h
new file mode 100644
index 0000000..5898fda
--- /dev/null
+++ b/runtime/simulator/code_simulator_arm64.h
@@ -0,0 +1,60 @@
+/*
+ * Copyright (C) 2015 The Android Open Source Project
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef ART_RUNTIME_SIMULATOR_CODE_SIMULATOR_ARM64_H_
+#define ART_RUNTIME_SIMULATOR_CODE_SIMULATOR_ARM64_H_
+
+#include "memory"
+#include "simulator/code_simulator.h"
+// TODO: make vixl clean wrt -Wshadow.
+#pragma GCC diagnostic push
+#pragma GCC diagnostic ignored "-Wunknown-pragmas"
+#pragma GCC diagnostic ignored "-Wshadow"
+#pragma GCC diagnostic ignored "-Wmissing-noreturn"
+#include "vixl/a64/simulator-a64.h"
+#pragma GCC diagnostic pop
+
+namespace art {
+namespace arm64 {
+
+class CodeSimulatorArm64 : public CodeSimulator {
+ public:
+  CodeSimulatorArm64();
+  virtual ~CodeSimulatorArm64();
+
+  static constexpr bool CanSimulateArm64() {
+    return kCanSimulate;
+  }
+
+  void RunFrom(intptr_t code_buffer) OVERRIDE;
+
+  bool GetCReturnBool() OVERRIDE;
+  int32_t GetCReturnInt32() OVERRIDE;
+  int64_t GetCReturnInt64() OVERRIDE;
+
+ private:
+  vixl::Decoder* decoder_;
+  vixl::Simulator* simulator_;
+
+  // TODO: Enable CodeSimulatorArm64 for more host ISAs once vixl::Simulator supports
+  // them.
+  static constexpr bool kCanSimulate = (kRuntimeISA == kX86_64);
+};
+
+}  // namespace arm64
+}  // namespace art
+
+#endif  // ART_RUNTIME_SIMULATOR_CODE_SIMULATOR_ARM64_H_