Suspend check reworking (ready for rewiew)
I hate burning a register, but the cost of suspend checks was just too high
in our current environment. There are things that can be done in future
releases to avoid the register burn, but for now it's worthwhile.
The general strategy is to reserve r4 as a suspend check counter.
Rather than poll the thread suspendPending counter, we instead simply
decrement the counter register. When it rolls to zero, we check. For
now I'm just using the counter scheme on backwards branches - we always
poll on returns (which is already heavyweight enough that the extra cost
isn't especially noticable).
I've also added an optimization hint to the MIR in case we have enough
time to test and enable the existing loop analysis code that omits the
suspend check on smallish counted loops.
Change-Id: I82d8bad5882a4cf2ccff590942e2d1520d58969d
diff --git a/src/compiler/codegen/arm/ArmLIR.h b/src/compiler/codegen/arm/ArmLIR.h
index 07e2e97..e436eea 100644
--- a/src/compiler/codegen/arm/ArmLIR.h
+++ b/src/compiler/codegen/arm/ArmLIR.h
@@ -28,7 +28,7 @@
* pointer in r0 as a hidden arg0. Otherwise used as codegen scratch
* registers.
* r0-r1: As in C/C++ r0 is 32-bit return register and r0/r1 is 64-bit
- * r4 : Callee save (promotion target)
+ * r4 : (rSUSPEND) is reserved (suspend check assist)
* r5 : Callee save (promotion target)
* r6 : Callee save (promotion target)
* r7 : Callee save (promotion target)
@@ -243,7 +243,7 @@
/*
* Annotate special-purpose core registers:
- * - VM: r4PC, r5FP, and r6SELF
+ * - VM: r6SELF
* - ARM architecture: r13sp, r14lr, and r15pc
*
* rPC, rFP, and rSELF are for architecture-independent code to use.
@@ -253,7 +253,7 @@
r1 = 1,
r2 = 2,
r3 = 3,
- r4 = 4,
+ rSUSPEND = 4,
r5 = 5,
r6 = 6,
r7 = 7,
@@ -366,6 +366,7 @@
* Assemble.c.
*/
typedef enum ArmOpcode {
+ kArmPseudoSuspendTarget = -15,
kArmPseudoThrowTarget = -14,
kArmPseudoCaseLabel = -13,
kArmPseudoMethodEntry = -12,