riscv64: Implement VarHandle.GetAndUpdate intrinsics.

Also fix `GenerateCompareAndSet()` to avoid ANDN inside
a LR/SC sequence as the instruction is not part of the
base "I" instruction set.

Test: testrunner.py --target --64 --ndebug --optimizing
Bug: 283082089
Change-Id: I09caa0486d9bedf93a40f0f15cab1e6bef19969c
3 files changed