Use 'final' and 'override' specifiers directly in ART.
Remove all uses of macros 'FINAL' and 'OVERRIDE' and replace them with
'final' and 'override' specifiers. Remove all definitions of these
macros as well, which were located in these files:
- libartbase/base/macros.h
- test/913-heaps/heaps.cc
- test/ti-agent/ti_macros.h
ART is now using C++14; the 'final' and 'override' specifiers have
been introduced in C++11.
Test: mmma art
Change-Id: I256c7758155a71a2940ef2574925a44076feeebf
diff --git a/disassembler/disassembler_arm.cc b/disassembler/disassembler_arm.cc
index 49f9249..c1a6f59 100644
--- a/disassembler/disassembler_arm.cc
+++ b/disassembler/disassembler_arm.cc
@@ -39,15 +39,15 @@
static const vixl::aarch32::Register tr(TR);
-class DisassemblerArm::CustomDisassembler FINAL : public PrintDisassembler {
- class CustomDisassemblerStream FINAL : public DisassemblerStream {
+class DisassemblerArm::CustomDisassembler final : public PrintDisassembler {
+ class CustomDisassemblerStream final : public DisassemblerStream {
public:
CustomDisassemblerStream(std::ostream& os,
const CustomDisassembler* disasm,
const DisassemblerOptions* options)
: DisassemblerStream(os), disasm_(disasm), options_(options) {}
- DisassemblerStream& operator<<(const PrintLabel& label) OVERRIDE {
+ DisassemblerStream& operator<<(const PrintLabel& label) override {
const LocationType type = label.GetLocationType();
switch (type) {
@@ -73,7 +73,7 @@
}
}
- DisassemblerStream& operator<<(vixl::aarch32::Register reg) OVERRIDE {
+ DisassemblerStream& operator<<(vixl::aarch32::Register reg) override {
if (reg.Is(tr)) {
os() << "tr";
return *this;
@@ -82,7 +82,7 @@
}
}
- DisassemblerStream& operator<<(const MemOperand& operand) OVERRIDE {
+ DisassemblerStream& operator<<(const MemOperand& operand) override {
// VIXL must use a PrintLabel object whenever the base register is PC;
// the following check verifies this invariant, and guards against bugs.
DCHECK(!operand.GetBaseRegister().Is(pc));
@@ -96,7 +96,7 @@
return *this;
}
- DisassemblerStream& operator<<(const vixl::aarch32::AlignedMemOperand& operand) OVERRIDE {
+ DisassemblerStream& operator<<(const vixl::aarch32::AlignedMemOperand& operand) override {
// VIXL must use a PrintLabel object whenever the base register is PC;
// the following check verifies this invariant, and guards against bugs.
DCHECK(!operand.GetBaseRegister().Is(pc));
@@ -116,7 +116,7 @@
disassembler_stream_(os, this, options),
is_t32_(true) {}
- void PrintCodeAddress(uint32_t prog_ctr) OVERRIDE {
+ void PrintCodeAddress(uint32_t prog_ctr) override {
os() << "0x" << std::hex << std::setw(8) << std::setfill('0') << prog_ctr << ": ";
}
diff --git a/disassembler/disassembler_arm.h b/disassembler/disassembler_arm.h
index 237b577..dd6621d 100644
--- a/disassembler/disassembler_arm.h
+++ b/disassembler/disassembler_arm.h
@@ -26,14 +26,14 @@
namespace art {
namespace arm {
-class DisassemblerArm FINAL : public Disassembler {
+class DisassemblerArm final : public Disassembler {
class CustomDisassembler;
public:
explicit DisassemblerArm(DisassemblerOptions* options);
- size_t Dump(std::ostream& os, const uint8_t* begin) OVERRIDE;
- void Dump(std::ostream& os, const uint8_t* begin, const uint8_t* end) OVERRIDE;
+ size_t Dump(std::ostream& os, const uint8_t* begin) override;
+ void Dump(std::ostream& os, const uint8_t* begin, const uint8_t* end) override;
private:
uintptr_t GetPc(uintptr_t instr_ptr) const {
diff --git a/disassembler/disassembler_arm64.h b/disassembler/disassembler_arm64.h
index 19e4dfb..89beaa9 100644
--- a/disassembler/disassembler_arm64.h
+++ b/disassembler/disassembler_arm64.h
@@ -29,7 +29,7 @@
namespace art {
namespace arm64 {
-class CustomDisassembler FINAL : public vixl::aarch64::Disassembler {
+class CustomDisassembler final : public vixl::aarch64::Disassembler {
public:
explicit CustomDisassembler(DisassemblerOptions* options)
: vixl::aarch64::Disassembler(),
@@ -45,13 +45,13 @@
// Use register aliases in the disassembly.
void AppendRegisterNameToOutput(const vixl::aarch64::Instruction* instr,
- const vixl::aarch64::CPURegister& reg) OVERRIDE;
+ const vixl::aarch64::CPURegister& reg) override;
// Improve the disassembly of literal load instructions.
- void VisitLoadLiteral(const vixl::aarch64::Instruction* instr) OVERRIDE;
+ void VisitLoadLiteral(const vixl::aarch64::Instruction* instr) override;
// Improve the disassembly of thread offset.
- void VisitLoadStoreUnsignedOffset(const vixl::aarch64::Instruction* instr) OVERRIDE;
+ void VisitLoadStoreUnsignedOffset(const vixl::aarch64::Instruction* instr) override;
private:
// Indicate if the disassembler should read data loaded from literal pools.
@@ -69,15 +69,15 @@
DisassemblerOptions* options_;
};
-class DisassemblerArm64 FINAL : public Disassembler {
+class DisassemblerArm64 final : public Disassembler {
public:
explicit DisassemblerArm64(DisassemblerOptions* options) :
Disassembler(options), disasm(options) {
decoder.AppendVisitor(&disasm);
}
- size_t Dump(std::ostream& os, const uint8_t* begin) OVERRIDE;
- void Dump(std::ostream& os, const uint8_t* begin, const uint8_t* end) OVERRIDE;
+ size_t Dump(std::ostream& os, const uint8_t* begin) override;
+ void Dump(std::ostream& os, const uint8_t* begin, const uint8_t* end) override;
private:
vixl::aarch64::Decoder decoder;
diff --git a/disassembler/disassembler_mips.h b/disassembler/disassembler_mips.h
index afa6af3..bc74b43 100644
--- a/disassembler/disassembler_mips.h
+++ b/disassembler/disassembler_mips.h
@@ -24,7 +24,7 @@
namespace art {
namespace mips {
-class DisassemblerMips FINAL : public Disassembler {
+class DisassemblerMips final : public Disassembler {
public:
explicit DisassemblerMips(DisassemblerOptions* options, bool is_o32_abi)
: Disassembler(options),
@@ -33,8 +33,8 @@
is_o32_abi_(is_o32_abi) {}
const char* RegName(uint32_t reg);
- size_t Dump(std::ostream& os, const uint8_t* begin) OVERRIDE;
- void Dump(std::ostream& os, const uint8_t* begin, const uint8_t* end) OVERRIDE;
+ size_t Dump(std::ostream& os, const uint8_t* begin) override;
+ void Dump(std::ostream& os, const uint8_t* begin, const uint8_t* end) override;
private:
// Address and encoding of the last disassembled instruction.
diff --git a/disassembler/disassembler_x86.h b/disassembler/disassembler_x86.h
index 31b62bc..a329280 100644
--- a/disassembler/disassembler_x86.h
+++ b/disassembler/disassembler_x86.h
@@ -24,13 +24,13 @@
enum RegFile { GPR, MMX, SSE };
-class DisassemblerX86 FINAL : public Disassembler {
+class DisassemblerX86 final : public Disassembler {
public:
DisassemblerX86(DisassemblerOptions* options, bool supports_rex)
: Disassembler(options), supports_rex_(supports_rex) {}
- size_t Dump(std::ostream& os, const uint8_t* begin) OVERRIDE;
- void Dump(std::ostream& os, const uint8_t* begin, const uint8_t* end) OVERRIDE;
+ size_t Dump(std::ostream& os, const uint8_t* begin) override;
+ void Dump(std::ostream& os, const uint8_t* begin, const uint8_t* end) override;
private:
size_t DumpNops(std::ostream& os, const uint8_t* instr);