commit b885d8b631ad0a72ade32cb6b07a2ddd062a664b
author Nicolas Geoffray <ngeoffray@google.com> Tue Jan 14 15:25:52 2020 +0000
committer Nicolas Geoffray <ngeoffray@google.com> Wed Jan 15 11:08:43 2020 +0000
tree 3199b2df453cb6e904b29cf316eeff51b3ece1fb
parent f676eb408593933c80fc336d9fd409015365fcb7

Surround MR uses with #if defined read barrier.

MR is only defined in the baker read barrier configuration.

Test: build with CMS configuration
Bug: 147094528
Change-Id: Ief13c74ac6706f82c065c3612d251fd52dcbc92e

runtime/arch/arm/quick_entrypoints_arm.S

diff --git a/runtime/arch/arm/quick_entrypoints_arm.S b/runtime/arch/arm/quick_entrypoints_arm.S
index 0609500..1b7038f 100644
--- a/runtime/arch/arm/quick_entrypoints_arm.S
+++ b/runtime/arch/arm/quick_entrypoints_arm.S
@@ -2735,9 +2735,11 @@
 #if (INLINE_CACHE_SIZE != 5)
 #error "INLINE_CACHE_SIZE not as expected."
 #endif
+#if defined(USE_READ_BARRIER) && defined(USE_BAKER_READ_BARRIER)
     // Don't update the cache if we are marking.
     cmp rMR, #0
     bne .Ldone
+#endif
 .Lentry1:
     ldr ip, [r4, #INLINE_CACHE_CLASSES_OFFSET]
     cmp ip, r0

runtime/arch/arm64/quick_entrypoints_arm64.S

diff --git a/runtime/arch/arm64/quick_entrypoints_arm64.S b/runtime/arch/arm64/quick_entrypoints_arm64.S
index f44f3e0..de5a069 100644
--- a/runtime/arch/arm64/quick_entrypoints_arm64.S
+++ b/runtime/arch/arm64/quick_entrypoints_arm64.S
@@ -2856,8 +2856,10 @@
 #if (INLINE_CACHE_SIZE != 5)
 #error "INLINE_CACHE_SIZE not as expected."
 #endif
+#if defined(USE_READ_BARRIER) && defined(USE_BAKER_READ_BARRIER)
     // Don't update the cache if we are marking.
     cbnz wMR, .Ldone
+#endif
 .Lentry1:
     ldr w9, [x8, #INLINE_CACHE_CLASSES_OFFSET]
     cmp w9, w0