riscv64: atomic fix for volatile sput
Test: Run these opcodes against all interpreter
tests on a Linux RISC-V VM.
(1) setup
lunch aosp_riscv64-userdebug
export ART_TEST_SSH_USER=ubuntu
export ART_TEST_SSH_HOST=localhost
export ART_TEST_SSH_PORT=10001
export ART_TEST_ON_VM=true
. art/tools/buildbot-utils.sh
art/tools/buildbot-build.sh --target
# Create, boot and configure the VM.
art/tools/buildbot-vm.sh create
art/tools/buildbot-vm.sh boot
art/tools/buildbot-vm.sh setup-ssh # password: 'ubuntu'
art/tools/buildbot-cleanup-device.sh
art/tools/buildbot-setup-device.sh
art/tools/buildbot-sync.sh
(2) test
art/test.py --target -r --no-prebuild --ndebug --64 -j 12 --cdex-none --interpreter
Bug: 283082047
Change-Id: I82a7869cb8ecf425106bb7314729d7ad20d69ef0
diff --git a/runtime/interpreter/mterp/riscv64/object.S b/runtime/interpreter/mterp/riscv64/object.S
index 8a64f64..a4afdd5 100644
--- a/runtime/interpreter/mterp/riscv64/object.S
+++ b/runtime/interpreter/mterp/riscv64/object.S
@@ -186,9 +186,11 @@
sh $value_reg, (t0)
fence rw, rw
.elseif $width == 32
- amoswap.w.rl $value_reg, $value_reg, (t0)
+ // value_reg must NOT be the destination register, the destination gets clobbered!
+ // For refs, value_reg's original value is used in the write barrier below.
+ amoswap.w.rl zero, $value_reg, (t0)
.else // width == 64
- amoswap.d.rl $value_reg, $value_reg, (t0)
+ amoswap.d.rl zero, $value_reg, (t0)
.endif // width
WRITE_BARRIER_IF_OBJECT $is_object, $value_reg, /*holder*/a0, /*uniq*/slow_${opcode}