Register promotion support for 64-bit targets
Not sufficiently tested for 64-bit targets, but should be
fairly close.
A significant amount of refactoring could stil be done, (in
later CLs).
With this change we are not making any changes to the vmap
scheme. As a result, it is a requirement that if a vreg
is promoted to both a 32-bit view and the low half of a
64-bit view it must share the same physical register. We
may change this restriction later on to allow for more flexibility
for 32-bit Arm.
For example, if v4, v5, v4/v5 and v5/v6 are all hot enough to
promote, we'd end up with something like:
v4 (as an int) -> r10
v4/v5 (as a long) -> r10
v5 (as an int) -> r11
v5/v6 (as a long) -> r11
Fix a couple of ARM64 bugs on the way...
Change-Id: I6a152b9c164d9f1a053622266e165428045362f3
diff --git a/compiler/dex/quick/mir_to_lir.cc b/compiler/dex/quick/mir_to_lir.cc
index 984e8ea..237288e 100644
--- a/compiler/dex/quick/mir_to_lir.cc
+++ b/compiler/dex/quick/mir_to_lir.cc
@@ -61,7 +61,7 @@
if (reg_arg_low.Valid()) {
LockTemp(reg_arg_low);
}
- if (reg_arg_high.Valid() && reg_arg_low != reg_arg_high) {
+ if (reg_arg_high.Valid() && reg_arg_low.NotExactlyEquals(reg_arg_high)) {
LockTemp(reg_arg_high);
}
}
@@ -249,7 +249,7 @@
LoadBaseDisp(reg_obj, data.field_offset, r_result, size, data.is_volatile ? kVolatile :
kNotVolatile);
}
- if (r_result != rl_dest.reg) {
+ if (r_result.NotExactlyEquals(rl_dest.reg)) {
if (wide) {
OpRegCopyWide(rl_dest.reg, r_result);
} else {