Revert^2 "Switch to LLVM prebuilt tools for ART gtests"
It is also necessary to adjust the expected output of some tests.
This reverts commit ea54b823a3a02f65c865e11bbbccb327a273c039.
Bug: 147817558
Test: m test-art-host-gtest
Change-Id: Ib244e8b7d43d575299654397a47056f295ab4589
diff --git a/compiler/utils/assembler_test_base.h b/compiler/utils/assembler_test_base.h
index 1567367..736a292 100644
--- a/compiler/utils/assembler_test_base.h
+++ b/compiler/utils/assembler_test_base.h
@@ -135,22 +135,24 @@
}
virtual std::vector<std::string> GetAssemblerCommand() {
- switch (GetIsa()) {
+ InstructionSet isa = GetIsa();
+ switch (isa) {
case InstructionSet::kX86:
- return {FindTool("as"), "--32"};
+ return {FindTool("clang"), "--compile", "-target", "i386-linux-gnu"};
case InstructionSet::kX86_64:
- return {FindTool("as"), "--64"};
+ return {FindTool("clang"), "--compile", "-target", "x86_64-linux-gnu"};
default:
- return {FindTool("as")};
+ LOG(FATAL) << "Unknown instruction set: " << isa;
+ UNREACHABLE();
}
}
virtual std::vector<std::string> GetDisassemblerCommand() {
switch (GetIsa()) {
case InstructionSet::kThumb2:
- return {FindTool("objdump"), "--disassemble", "-M", "force-thumb"};
+ return {FindTool("llvm-objdump"), "--disassemble", "-triple", "thumbv7a-linux-gnueabi"};
default:
- return {FindTool("objdump"), "--disassemble", "--no-show-raw-insn"};
+ return {FindTool("llvm-objdump"), "--disassemble", "--no-show-raw-insn"};
}
}
diff --git a/compiler/utils/assembler_thumb_test.cc b/compiler/utils/assembler_thumb_test.cc
index 72dfef1..1d9f013 100644
--- a/compiler/utils/assembler_thumb_test.cc
+++ b/compiler/utils/assembler_thumb_test.cc
@@ -18,8 +18,10 @@
#include <errno.h>
#include <string.h>
#include <sys/types.h>
+
#include <fstream>
#include <map>
+#include <regex>
#include "gtest/gtest.h"
@@ -51,10 +53,15 @@
std::string disassembly;
ASSERT_TRUE(Disassemble(obj_file, &disassembly));
+ // objdump on buildbot seems to sometimes add annotation like in "bne #226 <.text+0x1e8>".
+ // It is unclear why it does not reproduce locally. As work-around, remove the annotation.
+ std::regex annotation_re(" <\\.text\\+\\w+>");
+ disassembly = std::regex_replace(disassembly, annotation_re, "");
+
std::string expected2 = "\n" +
- obj_file + ": file format elf32-littlearm\n\n\n"
+ obj_file + ": file format ELF32-arm-little\n\n\n"
"Disassembly of section .text:\n\n"
- "00000000 <.text>:\n" +
+ "00000000 .text:\n" +
expected;
EXPECT_EQ(expected2, disassembly);
if (expected2 != disassembly) {
diff --git a/compiler/utils/assembler_thumb_test_expected.cc.inc b/compiler/utils/assembler_thumb_test_expected.cc.inc
index efe62c6..b2314c5 100644
--- a/compiler/utils/assembler_thumb_test_expected.cc.inc
+++ b/compiler/utils/assembler_thumb_test_expected.cc.inc
@@ -1,258 +1,258 @@
const char* const VixlJniHelpersResults = {
- " 0: e92d 4de0 stmdb sp!, {r5, r6, r7, r8, sl, fp, lr}\n"
- " 4: ed2d 8a10 vpush {s16-s31}\n"
- " 8: b089 sub sp, #36 ; 0x24\n"
- " a: 9000 str r0, [sp, #0]\n"
- " c: 9121 str r1, [sp, #132] ; 0x84\n"
- " e: ed8d 0a22 vstr s0, [sp, #136] ; 0x88\n"
- " 12: 9223 str r2, [sp, #140] ; 0x8c\n"
- " 14: 9324 str r3, [sp, #144] ; 0x90\n"
- " 16: b088 sub sp, #32\n"
- " 18: f5ad 5d80 sub.w sp, sp, #4096 ; 0x1000\n"
- " 1c: 9808 ldr r0, [sp, #32]\n"
- " 1e: 981f ldr r0, [sp, #124] ; 0x7c\n"
- " 20: 9821 ldr r0, [sp, #132] ; 0x84\n"
- " 22: 98ff ldr r0, [sp, #1020] ; 0x3fc\n"
- " 24: f8dd 0400 ldr.w r0, [sp, #1024] ; 0x400\n"
- " 28: f8dd cffc ldr.w ip, [sp, #4092] ; 0xffc\n"
- " 2c: f50d 5c80 add.w ip, sp, #4096 ; 0x1000\n"
- " 30: f8dc c000 ldr.w ip, [ip]\n"
- " 34: f8d9 c200 ldr.w ip, [r9, #512] ; 0x200\n"
- " 38: f8dc 0080 ldr.w r0, [ip, #128] ; 0x80\n"
- " 3c: 9008 str r0, [sp, #32]\n"
- " 3e: 901f str r0, [sp, #124] ; 0x7c\n"
- " 40: 9021 str r0, [sp, #132] ; 0x84\n"
- " 42: 90ff str r0, [sp, #1020] ; 0x3fc\n"
- " 44: f8cd 0400 str.w r0, [sp, #1024] ; 0x400\n"
- " 48: f8cd cffc str.w ip, [sp, #4092] ; 0xffc\n"
- " 4c: f84d 5d04 str.w r5, [sp, #-4]!\n"
- " 50: f50d 5580 add.w r5, sp, #4096 ; 0x1000\n"
- " 54: f8c5 c004 str.w ip, [r5, #4]\n"
- " 58: f85d 5b04 ldr.w r5, [sp], #4\n"
- " 5c: f04f 0cff mov.w ip, #255 ; 0xff\n"
- " 60: f8cd c030 str.w ip, [sp, #48] ; 0x30\n"
- " 64: f06f 4c7f mvn.w ip, #4278190080 ; 0xff000000\n"
- " 68: f8cd c030 str.w ip, [sp, #48] ; 0x30\n"
- " 6c: f8cd c030 str.w ip, [sp, #48] ; 0x30\n"
- " 70: f8cd c030 str.w ip, [sp, #48] ; 0x30\n"
- " 74: 900c str r0, [sp, #48] ; 0x30\n"
- " 76: f8dd c030 ldr.w ip, [sp, #48] ; 0x30\n"
- " 7a: f8cd c034 str.w ip, [sp, #52] ; 0x34\n"
- " 7e: f50d 5c80 add.w ip, sp, #4096 ; 0x1000\n"
- " 82: f8c9 c200 str.w ip, [r9, #512] ; 0x200\n"
- " 86: f8c9 d200 str.w sp, [r9, #512] ; 0x200\n"
- " 8a: f8d0 e030 ldr.w lr, [r0, #48] ; 0x30\n"
- " 8e: 47f0 blx lr\n"
- " 90: f8dd c02c ldr.w ip, [sp, #44] ; 0x2c\n"
- " 94: f8cd c030 str.w ip, [sp, #48] ; 0x30\n"
- " 98: f8d9 c200 ldr.w ip, [r9, #512] ; 0x200\n"
- " 9c: f8cd c02c str.w ip, [sp, #44] ; 0x2c\n"
- " a0: f8dd c02c ldr.w ip, [sp, #44] ; 0x2c\n"
- " a4: f8cd c030 str.w ip, [sp, #48] ; 0x30\n"
- " a8: 4648 mov r0, r9\n"
- " aa: f8cd 9030 str.w r9, [sp, #48] ; 0x30\n"
- " ae: 4604 mov r4, r0\n"
- " b0: f1bc 0f00 cmp.w ip, #0\n"
- " b4: bf18 it ne\n"
- " b6: f10d 0c30 addne.w ip, sp, #48 ; 0x30\n"
- " ba: f10d 0c30 add.w ip, sp, #48 ; 0x30\n"
- " be: f1bc 0f00 cmp.w ip, #0\n"
- " c2: bf0c ite eq\n"
- " c4: 2000 moveq r0, #0\n"
- " c6: a80c addne r0, sp, #48 ; 0x30\n"
- " c8: f8dd c040 ldr.w ip, [sp, #64] ; 0x40\n"
- " cc: f1bc 0f00 cmp.w ip, #0\n"
- " d0: bf18 it ne\n"
- " d2: f10d 0c40 addne.w ip, sp, #64 ; 0x40\n"
- " d6: f8cd c030 str.w ip, [sp, #48] ; 0x30\n"
- " da: f1bc 0f00 cmp.w ip, #0\n"
- " de: bf0c ite eq\n"
- " e0: 2000 moveq r0, #0\n"
- " e2: 4668 movne r0, sp\n"
- " e4: f1bc 0f00 cmp.w ip, #0\n"
- " e8: bf0c ite eq\n"
- " ea: 2000 moveq r0, #0\n"
- " ec: f20d 4001 addwne r0, sp, #1025 ; 0x401\n"
- " f0: f1bc 0f00 cmp.w ip, #0\n"
- " f4: bf18 it ne\n"
- " f6: f20d 4c01 addwne ip, sp, #1025 ; 0x401\n"
- " fa: f8d9 c0a4 ldr.w ip, [r9, #164] ; 0xa4\n"
- " fe: f1bc 0f00 cmp.w ip, #0\n"
- " 102: d171 bne.n 0x1e8\n"
- " 104: f8cd c7ff str.w ip, [sp, #2047] ; 0x7ff\n"
- " 108: f8cd c7ff str.w ip, [sp, #2047] ; 0x7ff\n"
- " 10c: f8cd c7ff str.w ip, [sp, #2047] ; 0x7ff\n"
- " 110: f8cd c7ff str.w ip, [sp, #2047] ; 0x7ff\n"
- " 114: f8cd c7ff str.w ip, [sp, #2047] ; 0x7ff\n"
- " 118: f8cd c7ff str.w ip, [sp, #2047] ; 0x7ff\n"
- " 11c: f8cd c7ff str.w ip, [sp, #2047] ; 0x7ff\n"
- " 120: f8cd c7ff str.w ip, [sp, #2047] ; 0x7ff\n"
- " 124: f8cd c7ff str.w ip, [sp, #2047] ; 0x7ff\n"
- " 128: f8cd c7ff str.w ip, [sp, #2047] ; 0x7ff\n"
- " 12c: f8cd c7ff str.w ip, [sp, #2047] ; 0x7ff\n"
- " 130: f8cd c7ff str.w ip, [sp, #2047] ; 0x7ff\n"
- " 134: f8cd c7ff str.w ip, [sp, #2047] ; 0x7ff\n"
- " 138: f8cd c7ff str.w ip, [sp, #2047] ; 0x7ff\n"
- " 13c: f8cd c7ff str.w ip, [sp, #2047] ; 0x7ff\n"
- " 140: f8cd c7ff str.w ip, [sp, #2047] ; 0x7ff\n"
- " 144: f8cd c7ff str.w ip, [sp, #2047] ; 0x7ff\n"
- " 148: f8cd c7ff str.w ip, [sp, #2047] ; 0x7ff\n"
- " 14c: f8cd c7ff str.w ip, [sp, #2047] ; 0x7ff\n"
- " 150: f8cd c7ff str.w ip, [sp, #2047] ; 0x7ff\n"
- " 154: f8cd c7ff str.w ip, [sp, #2047] ; 0x7ff\n"
- " 158: f8cd c7ff str.w ip, [sp, #2047] ; 0x7ff\n"
- " 15c: f8cd c7ff str.w ip, [sp, #2047] ; 0x7ff\n"
- " 160: f8cd c7ff str.w ip, [sp, #2047] ; 0x7ff\n"
- " 164: f8cd c7ff str.w ip, [sp, #2047] ; 0x7ff\n"
- " 168: f8cd c7ff str.w ip, [sp, #2047] ; 0x7ff\n"
- " 16c: f8cd c7ff str.w ip, [sp, #2047] ; 0x7ff\n"
- " 170: f8cd c7ff str.w ip, [sp, #2047] ; 0x7ff\n"
- " 174: f8cd c7ff str.w ip, [sp, #2047] ; 0x7ff\n"
- " 178: f8cd c7ff str.w ip, [sp, #2047] ; 0x7ff\n"
- " 17c: f8cd c7ff str.w ip, [sp, #2047] ; 0x7ff\n"
- " 180: f8cd c7ff str.w ip, [sp, #2047] ; 0x7ff\n"
- " 184: f8cd c7ff str.w ip, [sp, #2047] ; 0x7ff\n"
- " 188: f8cd c7ff str.w ip, [sp, #2047] ; 0x7ff\n"
- " 18c: f8cd c7ff str.w ip, [sp, #2047] ; 0x7ff\n"
- " 190: f8cd c7ff str.w ip, [sp, #2047] ; 0x7ff\n"
- " 194: f8cd c7ff str.w ip, [sp, #2047] ; 0x7ff\n"
- " 198: f8cd c7ff str.w ip, [sp, #2047] ; 0x7ff\n"
- " 19c: f8cd c7ff str.w ip, [sp, #2047] ; 0x7ff\n"
- " 1a0: f8cd c7ff str.w ip, [sp, #2047] ; 0x7ff\n"
- " 1a4: f8cd c7ff str.w ip, [sp, #2047] ; 0x7ff\n"
- " 1a8: f8cd c7ff str.w ip, [sp, #2047] ; 0x7ff\n"
- " 1ac: f8cd c7ff str.w ip, [sp, #2047] ; 0x7ff\n"
- " 1b0: f8cd c7ff str.w ip, [sp, #2047] ; 0x7ff\n"
- " 1b4: f8cd c7ff str.w ip, [sp, #2047] ; 0x7ff\n"
- " 1b8: f8cd c7ff str.w ip, [sp, #2047] ; 0x7ff\n"
- " 1bc: f8cd c7ff str.w ip, [sp, #2047] ; 0x7ff\n"
- " 1c0: f8cd c7ff str.w ip, [sp, #2047] ; 0x7ff\n"
- " 1c4: f8cd c7ff str.w ip, [sp, #2047] ; 0x7ff\n"
- " 1c8: f8cd c7ff str.w ip, [sp, #2047] ; 0x7ff\n"
- " 1cc: f8cd c7ff str.w ip, [sp, #2047] ; 0x7ff\n"
- " 1d0: f8cd c7ff str.w ip, [sp, #2047] ; 0x7ff\n"
- " 1d4: f8cd c7ff str.w ip, [sp, #2047] ; 0x7ff\n"
- " 1d8: f8cd c7ff str.w ip, [sp, #2047] ; 0x7ff\n"
- " 1dc: f8cd c7ff str.w ip, [sp, #2047] ; 0x7ff\n"
- " 1e0: f8cd c7ff str.w ip, [sp, #2047] ; 0x7ff\n"
- " 1e4: f000 b802 b.w 0x1ec\n"
- " 1e8: f000 b81b b.w 0x222\n"
- " 1ec: f8cd c7ff str.w ip, [sp, #2047] ; 0x7ff\n"
- " 1f0: f8cd c7ff str.w ip, [sp, #2047] ; 0x7ff\n"
- " 1f4: f8cd c7ff str.w ip, [sp, #2047] ; 0x7ff\n"
- " 1f8: f8cd c7ff str.w ip, [sp, #2047] ; 0x7ff\n"
- " 1fc: f8cd c7ff str.w ip, [sp, #2047] ; 0x7ff\n"
- " 200: f8cd c7ff str.w ip, [sp, #2047] ; 0x7ff\n"
- " 204: f8cd c7ff str.w ip, [sp, #2047] ; 0x7ff\n"
- " 208: f8cd c7ff str.w ip, [sp, #2047] ; 0x7ff\n"
- " 20c: f50d 5d80 add.w sp, sp, #4096 ; 0x1000\n"
- " 210: b008 add sp, #32\n"
- " 212: b009 add sp, #36 ; 0x24\n"
- " 214: ecbd 8a10 vpop {s16-s31}\n"
- " 218: e8bd 4de0 ldmia.w sp!, {r5, r6, r7, r8, sl, fp, lr}\n"
- " 21c: f8d9 8034 ldr.w r8, [r9, #52] ; 0x34\n"
- " 220: 4770 bx lr\n"
- " 222: 4660 mov r0, ip\n"
- " 224: f8d9 e2e8 ldr.w lr, [r9, #744] ; 0x2e8\n"
- " 228: 47f0 blx lr\n"
+ " 0: 2d e9 e0 4d push.w {r5, r6, r7, r8, r10, r11, lr}\n"
+ " 4: 2d ed 10 8a vpush {s16, s17, s18, s19, s20, s21, s22, s23, s24, s25, s26, s27, s28, s29, s30, s31}\n"
+ " 8: 89 b0 sub sp, #36\n"
+ " a: 00 90 str r0, [sp]\n"
+ " c: 21 91 str r1, [sp, #132]\n"
+ " e: 8d ed 22 0a vstr s0, [sp, #136]\n"
+ " 12: 23 92 str r2, [sp, #140]\n"
+ " 14: 24 93 str r3, [sp, #144]\n"
+ " 16: 88 b0 sub sp, #32\n"
+ " 18: ad f5 80 5d sub.w sp, sp, #4096\n"
+ " 1c: 08 98 ldr r0, [sp, #32]\n"
+ " 1e: 1f 98 ldr r0, [sp, #124]\n"
+ " 20: 21 98 ldr r0, [sp, #132]\n"
+ " 22: ff 98 ldr r0, [sp, #1020]\n"
+ " 24: dd f8 00 04 ldr.w r0, [sp, #1024]\n"
+ " 28: dd f8 fc cf ldr.w r12, [sp, #4092]\n"
+ " 2c: 0d f5 80 5c add.w r12, sp, #4096\n"
+ " 30: dc f8 00 c0 ldr.w r12, [r12]\n"
+ " 34: d9 f8 00 c2 ldr.w r12, [r9, #512]\n"
+ " 38: dc f8 80 00 ldr.w r0, [r12, #128]\n"
+ " 3c: 08 90 str r0, [sp, #32]\n"
+ " 3e: 1f 90 str r0, [sp, #124]\n"
+ " 40: 21 90 str r0, [sp, #132]\n"
+ " 42: ff 90 str r0, [sp, #1020]\n"
+ " 44: cd f8 00 04 str.w r0, [sp, #1024]\n"
+ " 48: cd f8 fc cf str.w r12, [sp, #4092]\n"
+ " 4c: 4d f8 04 5d str r5, [sp, #-4]!\n"
+ " 50: 0d f5 80 55 add.w r5, sp, #4096\n"
+ " 54: c5 f8 04 c0 str.w r12, [r5, #4]\n"
+ " 58: 5d f8 04 5b ldr r5, [sp], #4\n"
+ " 5c: 4f f0 ff 0c mov.w r12, #255\n"
+ " 60: cd f8 30 c0 str.w r12, [sp, #48]\n"
+ " 64: 6f f0 7f 4c mvn r12, #4278190080\n"
+ " 68: cd f8 30 c0 str.w r12, [sp, #48]\n"
+ " 6c: cd f8 30 c0 str.w r12, [sp, #48]\n"
+ " 70: cd f8 30 c0 str.w r12, [sp, #48]\n"
+ " 74: 0c 90 str r0, [sp, #48]\n"
+ " 76: dd f8 30 c0 ldr.w r12, [sp, #48]\n"
+ " 7a: cd f8 34 c0 str.w r12, [sp, #52]\n"
+ " 7e: 0d f5 80 5c add.w r12, sp, #4096\n"
+ " 82: c9 f8 00 c2 str.w r12, [r9, #512]\n"
+ " 86: c9 f8 00 d2 str.w sp, [r9, #512]\n"
+ " 8a: d0 f8 30 e0 ldr.w lr, [r0, #48]\n"
+ " 8e: f0 47 blx lr\n"
+ " 90: dd f8 2c c0 ldr.w r12, [sp, #44]\n"
+ " 94: cd f8 30 c0 str.w r12, [sp, #48]\n"
+ " 98: d9 f8 00 c2 ldr.w r12, [r9, #512]\n"
+ " 9c: cd f8 2c c0 str.w r12, [sp, #44]\n"
+ " a0: dd f8 2c c0 ldr.w r12, [sp, #44]\n"
+ " a4: cd f8 30 c0 str.w r12, [sp, #48]\n"
+ " a8: 48 46 mov r0, r9\n"
+ " aa: cd f8 30 90 str.w r9, [sp, #48]\n"
+ " ae: 04 46 mov r4, r0\n"
+ " b0: bc f1 00 0f cmp.w r12, #0\n"
+ " b4: 18 bf it ne\n"
+ " b6: 0d f1 30 0c addne.w r12, sp, #48\n"
+ " ba: 0d f1 30 0c add.w r12, sp, #48\n"
+ " be: bc f1 00 0f cmp.w r12, #0\n"
+ " c2: 0c bf ite eq\n"
+ " c4: 00 20 moveq r0, #0\n"
+ " c6: 0c a8 addne r0, sp, #48\n"
+ " c8: dd f8 40 c0 ldr.w r12, [sp, #64]\n"
+ " cc: bc f1 00 0f cmp.w r12, #0\n"
+ " d0: 18 bf it ne\n"
+ " d2: 0d f1 40 0c addne.w r12, sp, #64\n"
+ " d6: cd f8 30 c0 str.w r12, [sp, #48]\n"
+ " da: bc f1 00 0f cmp.w r12, #0\n"
+ " de: 0c bf ite eq\n"
+ " e0: 00 20 moveq r0, #0\n"
+ " e2: 68 46 movne r0, sp\n"
+ " e4: bc f1 00 0f cmp.w r12, #0\n"
+ " e8: 0c bf ite eq\n"
+ " ea: 00 20 moveq r0, #0\n"
+ " ec: 0d f2 01 40 addwne r0, sp, #1025\n"
+ " f0: bc f1 00 0f cmp.w r12, #0\n"
+ " f4: 18 bf it ne\n"
+ " f6: 0d f2 01 4c addwne r12, sp, #1025\n"
+ " fa: d9 f8 a4 c0 ldr.w r12, [r9, #164]\n"
+ " fe: bc f1 00 0f cmp.w r12, #0\n"
+ " 102: 71 d1 bne #226\n"
+ " 104: cd f8 ff c7 str.w r12, [sp, #2047]\n"
+ " 108: cd f8 ff c7 str.w r12, [sp, #2047]\n"
+ " 10c: cd f8 ff c7 str.w r12, [sp, #2047]\n"
+ " 110: cd f8 ff c7 str.w r12, [sp, #2047]\n"
+ " 114: cd f8 ff c7 str.w r12, [sp, #2047]\n"
+ " 118: cd f8 ff c7 str.w r12, [sp, #2047]\n"
+ " 11c: cd f8 ff c7 str.w r12, [sp, #2047]\n"
+ " 120: cd f8 ff c7 str.w r12, [sp, #2047]\n"
+ " 124: cd f8 ff c7 str.w r12, [sp, #2047]\n"
+ " 128: cd f8 ff c7 str.w r12, [sp, #2047]\n"
+ " 12c: cd f8 ff c7 str.w r12, [sp, #2047]\n"
+ " 130: cd f8 ff c7 str.w r12, [sp, #2047]\n"
+ " 134: cd f8 ff c7 str.w r12, [sp, #2047]\n"
+ " 138: cd f8 ff c7 str.w r12, [sp, #2047]\n"
+ " 13c: cd f8 ff c7 str.w r12, [sp, #2047]\n"
+ " 140: cd f8 ff c7 str.w r12, [sp, #2047]\n"
+ " 144: cd f8 ff c7 str.w r12, [sp, #2047]\n"
+ " 148: cd f8 ff c7 str.w r12, [sp, #2047]\n"
+ " 14c: cd f8 ff c7 str.w r12, [sp, #2047]\n"
+ " 150: cd f8 ff c7 str.w r12, [sp, #2047]\n"
+ " 154: cd f8 ff c7 str.w r12, [sp, #2047]\n"
+ " 158: cd f8 ff c7 str.w r12, [sp, #2047]\n"
+ " 15c: cd f8 ff c7 str.w r12, [sp, #2047]\n"
+ " 160: cd f8 ff c7 str.w r12, [sp, #2047]\n"
+ " 164: cd f8 ff c7 str.w r12, [sp, #2047]\n"
+ " 168: cd f8 ff c7 str.w r12, [sp, #2047]\n"
+ " 16c: cd f8 ff c7 str.w r12, [sp, #2047]\n"
+ " 170: cd f8 ff c7 str.w r12, [sp, #2047]\n"
+ " 174: cd f8 ff c7 str.w r12, [sp, #2047]\n"
+ " 178: cd f8 ff c7 str.w r12, [sp, #2047]\n"
+ " 17c: cd f8 ff c7 str.w r12, [sp, #2047]\n"
+ " 180: cd f8 ff c7 str.w r12, [sp, #2047]\n"
+ " 184: cd f8 ff c7 str.w r12, [sp, #2047]\n"
+ " 188: cd f8 ff c7 str.w r12, [sp, #2047]\n"
+ " 18c: cd f8 ff c7 str.w r12, [sp, #2047]\n"
+ " 190: cd f8 ff c7 str.w r12, [sp, #2047]\n"
+ " 194: cd f8 ff c7 str.w r12, [sp, #2047]\n"
+ " 198: cd f8 ff c7 str.w r12, [sp, #2047]\n"
+ " 19c: cd f8 ff c7 str.w r12, [sp, #2047]\n"
+ " 1a0: cd f8 ff c7 str.w r12, [sp, #2047]\n"
+ " 1a4: cd f8 ff c7 str.w r12, [sp, #2047]\n"
+ " 1a8: cd f8 ff c7 str.w r12, [sp, #2047]\n"
+ " 1ac: cd f8 ff c7 str.w r12, [sp, #2047]\n"
+ " 1b0: cd f8 ff c7 str.w r12, [sp, #2047]\n"
+ " 1b4: cd f8 ff c7 str.w r12, [sp, #2047]\n"
+ " 1b8: cd f8 ff c7 str.w r12, [sp, #2047]\n"
+ " 1bc: cd f8 ff c7 str.w r12, [sp, #2047]\n"
+ " 1c0: cd f8 ff c7 str.w r12, [sp, #2047]\n"
+ " 1c4: cd f8 ff c7 str.w r12, [sp, #2047]\n"
+ " 1c8: cd f8 ff c7 str.w r12, [sp, #2047]\n"
+ " 1cc: cd f8 ff c7 str.w r12, [sp, #2047]\n"
+ " 1d0: cd f8 ff c7 str.w r12, [sp, #2047]\n"
+ " 1d4: cd f8 ff c7 str.w r12, [sp, #2047]\n"
+ " 1d8: cd f8 ff c7 str.w r12, [sp, #2047]\n"
+ " 1dc: cd f8 ff c7 str.w r12, [sp, #2047]\n"
+ " 1e0: cd f8 ff c7 str.w r12, [sp, #2047]\n"
+ " 1e4: 00 f0 02 b8 b.w #4\n"
+ " 1e8: 00 f0 1b b8 b.w #54\n"
+ " 1ec: cd f8 ff c7 str.w r12, [sp, #2047]\n"
+ " 1f0: cd f8 ff c7 str.w r12, [sp, #2047]\n"
+ " 1f4: cd f8 ff c7 str.w r12, [sp, #2047]\n"
+ " 1f8: cd f8 ff c7 str.w r12, [sp, #2047]\n"
+ " 1fc: cd f8 ff c7 str.w r12, [sp, #2047]\n"
+ " 200: cd f8 ff c7 str.w r12, [sp, #2047]\n"
+ " 204: cd f8 ff c7 str.w r12, [sp, #2047]\n"
+ " 208: cd f8 ff c7 str.w r12, [sp, #2047]\n"
+ " 20c: 0d f5 80 5d add.w sp, sp, #4096\n"
+ " 210: 08 b0 add sp, #32\n"
+ " 212: 09 b0 add sp, #36\n"
+ " 214: bd ec 10 8a vpop {s16, s17, s18, s19, s20, s21, s22, s23, s24, s25, s26, s27, s28, s29, s30, s31}\n"
+ " 218: bd e8 e0 4d pop.w {r5, r6, r7, r8, r10, r11, lr}\n"
+ " 21c: d9 f8 34 80 ldr.w r8, [r9, #52]\n"
+ " 220: 70 47 bx lr\n"
+ " 222: 60 46 mov r0, r12\n"
+ " 224: d9 f8 e8 e2 ldr.w lr, [r9, #744]\n"
+ " 228: f0 47 blx lr\n"
};
const char* const VixlLoadFromOffsetResults = {
- " 0: 68e2 ldr r2, [r4, #12]\n"
- " 2: f8d4 2fff ldr.w r2, [r4, #4095] ; 0xfff\n"
- " 6: f504 5280 add.w r2, r4, #4096 ; 0x1000\n"
- " a: 6812 ldr r2, [r2, #0]\n"
- " c: f504 1280 add.w r2, r4, #1048576 ; 0x100000\n"
- " 10: f8d2 20a4 ldr.w r2, [r2, #164] ; 0xa4\n"
- " 14: f44f 5280 mov.w r2, #4096 ; 0x1000\n"
- " 18: f2c0 0210 movt r2, #16\n"
- " 1c: 4422 add r2, r4\n"
- " 1e: 6812 ldr r2, [r2, #0]\n"
- " 20: f44f 5c80 mov.w ip, #4096 ; 0x1000\n"
- " 24: f2c0 0c10 movt ip, #16\n"
- " 28: 4464 add r4, ip\n"
- " 2a: 6824 ldr r4, [r4, #0]\n"
- " 2c: 89a2 ldrh r2, [r4, #12]\n"
- " 2e: f8b4 2fff ldrh.w r2, [r4, #4095] ; 0xfff\n"
- " 32: f504 5280 add.w r2, r4, #4096 ; 0x1000\n"
- " 36: 8812 ldrh r2, [r2, #0]\n"
- " 38: f504 1280 add.w r2, r4, #1048576 ; 0x100000\n"
- " 3c: f8b2 20a4 ldrh.w r2, [r2, #164] ; 0xa4\n"
- " 40: f44f 5280 mov.w r2, #4096 ; 0x1000\n"
- " 44: f2c0 0210 movt r2, #16\n"
- " 48: 4422 add r2, r4\n"
- " 4a: 8812 ldrh r2, [r2, #0]\n"
- " 4c: f44f 5c80 mov.w ip, #4096 ; 0x1000\n"
- " 50: f2c0 0c10 movt ip, #16\n"
- " 54: 4464 add r4, ip\n"
- " 56: 8824 ldrh r4, [r4, #0]\n"
- " 58: e9d4 2303 ldrd r2, r3, [r4, #12]\n"
- " 5c: e9d4 23ff ldrd r2, r3, [r4, #1020] ; 0x3fc\n"
- " 60: f504 6280 add.w r2, r4, #1024 ; 0x400\n"
- " 64: e9d2 2300 ldrd r2, r3, [r2]\n"
- " 68: f504 2280 add.w r2, r4, #262144 ; 0x40000\n"
- " 6c: e9d2 2329 ldrd r2, r3, [r2, #164] ; 0xa4\n"
- " 70: f44f 6280 mov.w r2, #1024 ; 0x400\n"
- " 74: f2c0 0204 movt r2, #4\n"
- " 78: 4422 add r2, r4\n"
- " 7a: e9d2 2300 ldrd r2, r3, [r2]\n"
- " 7e: f44f 6c80 mov.w ip, #1024 ; 0x400\n"
- " 82: f2c0 0c04 movt ip, #4\n"
- " 86: 4464 add r4, ip\n"
- " 88: e9d4 4500 ldrd r4, r5, [r4]\n"
- " 8c: f8dc 000c ldr.w r0, [ip, #12]\n"
- " 90: f5a4 1280 sub.w r2, r4, #1048576 ; 0x100000\n"
- " 94: f8d2 20a4 ldr.w r2, [r2, #164] ; 0xa4\n"
- " 98: f994 200c ldrsb.w r2, [r4, #12]\n"
- " 9c: 7b22 ldrb r2, [r4, #12]\n"
- " 9e: f9b4 200c ldrsh.w r2, [r4, #12]\n"
+ " 0: e2 68 ldr r2, [r4, #12]\n"
+ " 2: d4 f8 ff 2f ldr.w r2, [r4, #4095]\n"
+ " 6: 04 f5 80 52 add.w r2, r4, #4096\n"
+ " a: 12 68 ldr r2, [r2]\n"
+ " c: 04 f5 80 12 add.w r2, r4, #1048576\n"
+ " 10: d2 f8 a4 20 ldr.w r2, [r2, #164]\n"
+ " 14: 4f f4 80 52 mov.w r2, #4096\n"
+ " 18: c0 f2 10 02 movt r2, #16\n"
+ " 1c: 22 44 add r2, r4\n"
+ " 1e: 12 68 ldr r2, [r2]\n"
+ " 20: 4f f4 80 5c mov.w r12, #4096\n"
+ " 24: c0 f2 10 0c movt r12, #16\n"
+ " 28: 64 44 add r4, r12\n"
+ " 2a: 24 68 ldr r4, [r4]\n"
+ " 2c: a2 89 ldrh r2, [r4, #12]\n"
+ " 2e: b4 f8 ff 2f ldrh.w r2, [r4, #4095]\n"
+ " 32: 04 f5 80 52 add.w r2, r4, #4096\n"
+ " 36: 12 88 ldrh r2, [r2]\n"
+ " 38: 04 f5 80 12 add.w r2, r4, #1048576\n"
+ " 3c: b2 f8 a4 20 ldrh.w r2, [r2, #164]\n"
+ " 40: 4f f4 80 52 mov.w r2, #4096\n"
+ " 44: c0 f2 10 02 movt r2, #16\n"
+ " 48: 22 44 add r2, r4\n"
+ " 4a: 12 88 ldrh r2, [r2]\n"
+ " 4c: 4f f4 80 5c mov.w r12, #4096\n"
+ " 50: c0 f2 10 0c movt r12, #16\n"
+ " 54: 64 44 add r4, r12\n"
+ " 56: 24 88 ldrh r4, [r4]\n"
+ " 58: d4 e9 03 23 ldrd r2, r3, [r4, #12]\n"
+ " 5c: d4 e9 ff 23 ldrd r2, r3, [r4, #1020]\n"
+ " 60: 04 f5 80 62 add.w r2, r4, #1024\n"
+ " 64: d2 e9 00 23 ldrd r2, r3, [r2]\n"
+ " 68: 04 f5 80 22 add.w r2, r4, #262144\n"
+ " 6c: d2 e9 29 23 ldrd r2, r3, [r2, #164]\n"
+ " 70: 4f f4 80 62 mov.w r2, #1024\n"
+ " 74: c0 f2 04 02 movt r2, #4\n"
+ " 78: 22 44 add r2, r4\n"
+ " 7a: d2 e9 00 23 ldrd r2, r3, [r2]\n"
+ " 7e: 4f f4 80 6c mov.w r12, #1024\n"
+ " 82: c0 f2 04 0c movt r12, #4\n"
+ " 86: 64 44 add r4, r12\n"
+ " 88: d4 e9 00 45 ldrd r4, r5, [r4]\n"
+ " 8c: dc f8 0c 00 ldr.w r0, [r12, #12]\n"
+ " 90: a4 f5 80 12 sub.w r2, r4, #1048576\n"
+ " 94: d2 f8 a4 20 ldr.w r2, [r2, #164]\n"
+ " 98: 94 f9 0c 20 ldrsb.w r2, [r4, #12]\n"
+ " 9c: 22 7b ldrb r2, [r4, #12]\n"
+ " 9e: b4 f9 0c 20 ldrsh.w r2, [r4, #12]\n"
};
const char* const VixlStoreToOffsetResults = {
- " 0: 60e2 str r2, [r4, #12]\n"
- " 2: f8c4 2fff str.w r2, [r4, #4095] ; 0xfff\n"
- " 6: f504 5c80 add.w ip, r4, #4096 ; 0x1000\n"
- " a: f8cc 2000 str.w r2, [ip]\n"
- " e: f504 1c80 add.w ip, r4, #1048576 ; 0x100000\n"
- " 12: f8cc 20a4 str.w r2, [ip, #164] ; 0xa4\n"
- " 16: f44f 5c80 mov.w ip, #4096 ; 0x1000\n"
- " 1a: f2c0 0c10 movt ip, #16\n"
- " 1e: 44a4 add ip, r4\n"
- " 20: f8cc 2000 str.w r2, [ip]\n"
- " 24: f44f 5c80 mov.w ip, #4096 ; 0x1000\n"
- " 28: f2c0 0c10 movt ip, #16\n"
- " 2c: 44a4 add ip, r4\n"
- " 2e: f8cc 4000 str.w r4, [ip]\n"
- " 32: 81a2 strh r2, [r4, #12]\n"
- " 34: f8a4 2fff strh.w r2, [r4, #4095] ; 0xfff\n"
- " 38: f504 5c80 add.w ip, r4, #4096 ; 0x1000\n"
- " 3c: f8ac 2000 strh.w r2, [ip]\n"
- " 40: f504 1c80 add.w ip, r4, #1048576 ; 0x100000\n"
- " 44: f8ac 20a4 strh.w r2, [ip, #164] ; 0xa4\n"
- " 48: f44f 5c80 mov.w ip, #4096 ; 0x1000\n"
- " 4c: f2c0 0c10 movt ip, #16\n"
- " 50: 44a4 add ip, r4\n"
- " 52: f8ac 2000 strh.w r2, [ip]\n"
- " 56: f44f 5c80 mov.w ip, #4096 ; 0x1000\n"
- " 5a: f2c0 0c10 movt ip, #16\n"
- " 5e: 44a4 add ip, r4\n"
- " 60: f8ac 4000 strh.w r4, [ip]\n"
- " 64: e9c4 2303 strd r2, r3, [r4, #12]\n"
- " 68: e9c4 23ff strd r2, r3, [r4, #1020] ; 0x3fc\n"
- " 6c: f504 6c80 add.w ip, r4, #1024 ; 0x400\n"
- " 70: e9cc 2300 strd r2, r3, [ip]\n"
- " 74: f504 2c80 add.w ip, r4, #262144 ; 0x40000\n"
- " 78: e9cc 2329 strd r2, r3, [ip, #164] ; 0xa4\n"
- " 7c: f44f 6c80 mov.w ip, #1024 ; 0x400\n"
- " 80: f2c0 0c04 movt ip, #4\n"
- " 84: 44a4 add ip, r4\n"
- " 86: e9cc 2300 strd r2, r3, [ip]\n"
- " 8a: f44f 6c80 mov.w ip, #1024 ; 0x400\n"
- " 8e: f2c0 0c04 movt ip, #4\n"
- " 92: 44a4 add ip, r4\n"
- " 94: e9cc 4500 strd r4, r5, [ip]\n"
- " 98: f8cc 000c str.w r0, [ip, #12]\n"
- " 9c: f5a4 1c80 sub.w ip, r4, #1048576 ; 0x100000\n"
- " a0: f8cc 20a4 str.w r2, [ip, #164] ; 0xa4\n"
- " a4: 7322 strb r2, [r4, #12]\n"
+ " 0: e2 60 str r2, [r4, #12]\n"
+ " 2: c4 f8 ff 2f str.w r2, [r4, #4095]\n"
+ " 6: 04 f5 80 5c add.w r12, r4, #4096\n"
+ " a: cc f8 00 20 str.w r2, [r12]\n"
+ " e: 04 f5 80 1c add.w r12, r4, #1048576\n"
+ " 12: cc f8 a4 20 str.w r2, [r12, #164]\n"
+ " 16: 4f f4 80 5c mov.w r12, #4096\n"
+ " 1a: c0 f2 10 0c movt r12, #16\n"
+ " 1e: a4 44 add r12, r4\n"
+ " 20: cc f8 00 20 str.w r2, [r12]\n"
+ " 24: 4f f4 80 5c mov.w r12, #4096\n"
+ " 28: c0 f2 10 0c movt r12, #16\n"
+ " 2c: a4 44 add r12, r4\n"
+ " 2e: cc f8 00 40 str.w r4, [r12]\n"
+ " 32: a2 81 strh r2, [r4, #12]\n"
+ " 34: a4 f8 ff 2f strh.w r2, [r4, #4095]\n"
+ " 38: 04 f5 80 5c add.w r12, r4, #4096\n"
+ " 3c: ac f8 00 20 strh.w r2, [r12]\n"
+ " 40: 04 f5 80 1c add.w r12, r4, #1048576\n"
+ " 44: ac f8 a4 20 strh.w r2, [r12, #164]\n"
+ " 48: 4f f4 80 5c mov.w r12, #4096\n"
+ " 4c: c0 f2 10 0c movt r12, #16\n"
+ " 50: a4 44 add r12, r4\n"
+ " 52: ac f8 00 20 strh.w r2, [r12]\n"
+ " 56: 4f f4 80 5c mov.w r12, #4096\n"
+ " 5a: c0 f2 10 0c movt r12, #16\n"
+ " 5e: a4 44 add r12, r4\n"
+ " 60: ac f8 00 40 strh.w r4, [r12]\n"
+ " 64: c4 e9 03 23 strd r2, r3, [r4, #12]\n"
+ " 68: c4 e9 ff 23 strd r2, r3, [r4, #1020]\n"
+ " 6c: 04 f5 80 6c add.w r12, r4, #1024\n"
+ " 70: cc e9 00 23 strd r2, r3, [r12]\n"
+ " 74: 04 f5 80 2c add.w r12, r4, #262144\n"
+ " 78: cc e9 29 23 strd r2, r3, [r12, #164]\n"
+ " 7c: 4f f4 80 6c mov.w r12, #1024\n"
+ " 80: c0 f2 04 0c movt r12, #4\n"
+ " 84: a4 44 add r12, r4\n"
+ " 86: cc e9 00 23 strd r2, r3, [r12]\n"
+ " 8a: 4f f4 80 6c mov.w r12, #1024\n"
+ " 8e: c0 f2 04 0c movt r12, #4\n"
+ " 92: a4 44 add r12, r4\n"
+ " 94: cc e9 00 45 strd r4, r5, [r12]\n"
+ " 98: cc f8 0c 00 str.w r0, [r12, #12]\n"
+ " 9c: a4 f5 80 1c sub.w r12, r4, #1048576\n"
+ " a0: cc f8 a4 20 str.w r2, [r12, #164]\n"
+ " a4: 22 73 strb r2, [r4, #12]\n"
};
diff --git a/compiler/utils/x86_64/assembler_x86_64_test.cc b/compiler/utils/x86_64/assembler_x86_64_test.cc
index 30f5ef2..7d196bd 100644
--- a/compiler/utils/x86_64/assembler_x86_64_test.cc
+++ b/compiler/utils/x86_64/assembler_x86_64_test.cc
@@ -947,7 +947,7 @@
}
TEST_F(AssemblerX86_64Test, Xchgq) {
- DriverStr(RepeatRR(&x86_64::X86_64Assembler::xchgq, "xchgq %{reg2}, %{reg1}"), "xchgq");
+ DriverStr(RepeatRR(&x86_64::X86_64Assembler::xchgq, "xchgq %{reg1}, %{reg2}"), "xchgq");
}
TEST_F(AssemblerX86_64Test, Xchgl) {
@@ -1123,7 +1123,7 @@
}
TEST_F(AssemblerX86_64Test, Movsxd) {
- DriverStr(RepeatRr(&x86_64::X86_64Assembler::movsxd, "movsxd %{reg2}, %{reg1}"), "movsxd");
+ DriverStr(RepeatRr(&x86_64::X86_64Assembler::movsxd, "movslq %{reg2}, %{reg1}"), "movsxd");
}
TEST_F(AssemblerX86_64Test, Movaps) {