Enable compiler_test on host.
Change-Id: I67a745ba78567af6c967cc44cd9c9640ef5ba398
diff --git a/src/compiler/Frontend.cc b/src/compiler/Frontend.cc
index 6ccccd2..cca891d 100644
--- a/src/compiler/Frontend.cc
+++ b/src/compiler/Frontend.cc
@@ -786,6 +786,10 @@
cUnit->enableDebug = compilerDebugFlags;
cUnit->printMe = VLOG_IS_ON(compiler) || (cUnit->enableDebug & (1 << kDebugVerbose));
}
+ if (cUnit->instructionSet == kX86) {
+ // Disable optimizations on X86 for now
+ cUnit->disableOpt = -1;
+ }
/* Are we generating code for the debugger? */
if (compiler.IsDebuggingSupported()) {
cUnit->genDebugger = true;
diff --git a/src/compiler/codegen/CodegenUtil.cc b/src/compiler/codegen/CodegenUtil.cc
index d4b8eea..0226fac 100644
--- a/src/compiler/codegen/CodegenUtil.cc
+++ b/src/compiler/codegen/CodegenUtil.cc
@@ -291,16 +291,16 @@
break;
case kPseudoTargetLabel:
case kPseudoNormalBlockLabel:
- LOG(INFO) << "L" << (intptr_t)lir << ":";
+ LOG(INFO) << "L" << (void*)lir << ":";
break;
case kPseudoThrowTarget:
- LOG(INFO) << "LT" << (intptr_t)lir << ":";
+ LOG(INFO) << "LT" << (void*)lir << ":";
break;
case kPseudoSuspendTarget:
- LOG(INFO) << "LS" << (intptr_t)lir << ":";
+ LOG(INFO) << "LS" << (void*)lir << ":";
break;
case kPseudoCaseLabel:
- LOG(INFO) << "LC" << (intptr_t)lir << ": Case target 0x" <<
+ LOG(INFO) << "LC" << (void*)lir << ": Case target 0x" <<
std::hex << lir->operands[0] << "|" << std::dec <<
lir->operands[0];
break;
diff --git a/src/compiler/codegen/GenInvoke.cc b/src/compiler/codegen/GenInvoke.cc
index c2023ff..2810936 100644
--- a/src/compiler/codegen/GenInvoke.cc
+++ b/src/compiler/codegen/GenInvoke.cc
@@ -52,11 +52,12 @@
if (cUnit->numIns == 0)
return;
- int firstArgReg = rARG1;
#if !defined(TARGET_X86)
- int lastArgReg = rARG3;
+ const int numArgRegs = 3;
+ static int argRegs[] = {rARG1, rARG2, rARG3};
#else
- int lastArgReg = rARG2;
+ const int numArgRegs = 2;
+ static int argRegs[] = {rARG1, rARG2};
#endif
int startVReg = cUnit->numDalvikRegisters - cUnit->numIns;
/*
@@ -73,15 +74,15 @@
*/
for (int i = 0; i < cUnit->numIns; i++) {
PromotionMap* vMap = &cUnit->promotionMap[startVReg + i];
- if (i <= (lastArgReg - firstArgReg)) {
+ if (i < numArgRegs) {
// If arriving in register
bool needFlush = true;
RegLocation* tLoc = &cUnit->regLocation[startVReg + i];
if ((vMap->coreLocation == kLocPhysReg) && !tLoc->fp) {
- opRegCopy(cUnit, vMap->coreReg, firstArgReg + i);
+ opRegCopy(cUnit, vMap->coreReg, argRegs[i]);
needFlush = false;
} else if ((vMap->fpLocation == kLocPhysReg) && tLoc->fp) {
- opRegCopy(cUnit, vMap->fpReg, firstArgReg + i);
+ opRegCopy(cUnit, vMap->fpReg, argRegs[i]);
needFlush = false;
} else {
needFlush = true;
@@ -95,7 +96,7 @@
}
if (needFlush) {
storeBaseDisp(cUnit, rSP, oatSRegOffset(cUnit, startVReg + i),
- firstArgReg + i, kWord);
+ argRegs[i], kWord);
}
} else {
// If arriving in frame & promoted
diff --git a/src/compiler/codegen/x86/ArchUtility.cc b/src/compiler/codegen/x86/ArchUtility.cc
index 9830e13..a5987f2 100644
--- a/src/compiler/codegen/x86/ArchUtility.cc
+++ b/src/compiler/codegen/x86/ArchUtility.cc
@@ -72,6 +72,10 @@
DCHECK_LT(i, fmt_len);
int operand = lir->operands[operand_number];
switch(fmt[i]) {
+ case 'c':
+ DCHECK_LT(static_cast<size_t>(operand), sizeof(x86CondName));
+ buf += x86CondName[operand];
+ break;
case 'd':
buf += StringPrintf("%d", operand);
break;
@@ -84,9 +88,10 @@
buf += x86RegName[operand];
}
break;
- case 'c':
- DCHECK_LT(static_cast<size_t>(operand), sizeof(x86CondName));
- buf += x86CondName[operand];
+ case 't':
+ buf += StringPrintf("0x%08x (L%p)",
+ (intptr_t)baseAddr + lir->offset + operand,
+ lir->target);
break;
default:
buf += StringPrintf("DecodeError '%c'", fmt[i]);
diff --git a/src/compiler/codegen/x86/Assemble.cc b/src/compiler/codegen/x86/Assemble.cc
index d64db02..d2a33ea 100644
--- a/src/compiler/codegen/x86/Assemble.cc
+++ b/src/compiler/codegen/x86/Assemble.cc
@@ -29,100 +29,100 @@
{ kX86Bkpt, kNullary, NO_OPERAND | IS_BRANCH, { 0, 0, 0xCC, 0, 0, 0, 0, 4 }, "int 3", "" },
{ kX86Nop, kNop, IS_UNARY_OP, { 0, 0, 0x90, 0, 0, 0, 0, 0 }, "nop", "" },
-#define ENCODING_MAP(opname, \
+#define ENCODING_MAP(opname, is_store, \
rm8_r8, rm32_r32, \
r8_rm8, r32_rm32, \
ax8_i8, ax32_i32, \
rm8_i8, rm8_i8_modrm, \
rm32_i32, rm32_i32_modrm, \
rm32_i8, rm32_i8_modrm) \
-{ kX86 ## opname ## 8MR, kMemReg, IS_STORE | IS_TERTIARY_OP | SETS_CCODES, { 0, 0, rm8_r8, 0, 0, 0, 0, 0 }, #opname "8MR", "[!0r+!1d],!2r" }, \
-{ kX86 ## opname ## 8AR, kArrayReg, IS_STORE | IS_QUIN_OP | SETS_CCODES, { 0, 0, rm8_r8, 0, 0, 0, 0, 0 }, #opname "8AR", "[!0r+!1r<<!2d+!3d],!4r" }, \
-{ kX86 ## opname ## 8TR, kThreadReg,IS_STORE | IS_BINARY_OP | SETS_CCODES, { THREAD_PREFIX, 0, rm8_r8, 0, 0, 0, 0, 0 }, #opname "8TR", "fs:[!0d],!1r" }, \
+{ kX86 ## opname ## 8MR, kMemReg, is_store | IS_TERTIARY_OP | SETS_CCODES, { 0, 0, rm8_r8, 0, 0, 0, 0, 0 }, #opname "8MR", "[!0r+!1d],!2r" }, \
+{ kX86 ## opname ## 8AR, kArrayReg, is_store | IS_QUIN_OP | SETS_CCODES, { 0, 0, rm8_r8, 0, 0, 0, 0, 0 }, #opname "8AR", "[!0r+!1r<<!2d+!3d],!4r" }, \
+{ kX86 ## opname ## 8TR, kThreadReg,is_store | IS_BINARY_OP | SETS_CCODES, { THREAD_PREFIX, 0, rm8_r8, 0, 0, 0, 0, 0 }, #opname "8TR", "fs:[!0d],!1r" }, \
{ kX86 ## opname ## 8RR, kRegReg, IS_BINARY_OP | SETS_CCODES, { 0, 0, r8_rm8, 0, 0, 0, 0, 0 }, #opname "8RR", "!0r,!1r" }, \
{ kX86 ## opname ## 8RM, kRegMem, IS_LOAD | IS_TERTIARY_OP | SETS_CCODES, { 0, 0, r8_rm8, 0, 0, 0, 0, 0 }, #opname "8RM", "!0r,[!1r+!2d]" }, \
{ kX86 ## opname ## 8RA, kRegArray, IS_LOAD | IS_QUIN_OP | SETS_CCODES, { 0, 0, r8_rm8, 0, 0, 0, 0, 0 }, #opname "8RA", "!0r,[!1r+!2r<<!3d+!4d]" }, \
{ kX86 ## opname ## 8RT, kRegThread, IS_LOAD | IS_BINARY_OP | SETS_CCODES, { THREAD_PREFIX, 0, r8_rm8, 0, 0, 0, 0, 0 }, #opname "8RT", "!0r,fs:[!1d]" }, \
{ kX86 ## opname ## 8RI, kRegImm, IS_BINARY_OP | SETS_CCODES, { 0, 0, rm8_i8, 0, 0, rm8_i8_modrm, ax8_i8, 1 }, #opname "8RI", "!0r,!1d" }, \
-{ kX86 ## opname ## 8MI, kMemImm, IS_STORE | IS_TERTIARY_OP | SETS_CCODES, { 0, 0, rm8_i8, 0, 0, rm8_i8_modrm, 0, 1 }, #opname "8MI", "[!0r+!1d],!2r" }, \
-{ kX86 ## opname ## 8AI, kArrayImm, IS_STORE | IS_QUIN_OP | SETS_CCODES, { 0, 0, rm8_i8, 0, 0, rm8_i8_modrm, 0, 1 }, #opname "8AI", "[!0r+!1r<<!2d+!3d],!4r" }, \
-{ kX86 ## opname ## 8TI, kThreadImm,IS_STORE | IS_BINARY_OP | SETS_CCODES, { THREAD_PREFIX, 0, rm8_i8, 0, 0, rm8_i8_modrm, 0, 1 }, #opname "8TI", "fs:[!0d],!1r" }, \
+{ kX86 ## opname ## 8MI, kMemImm, is_store | IS_TERTIARY_OP | SETS_CCODES, { 0, 0, rm8_i8, 0, 0, rm8_i8_modrm, 0, 1 }, #opname "8MI", "[!0r+!1d],!2r" }, \
+{ kX86 ## opname ## 8AI, kArrayImm, is_store | IS_QUIN_OP | SETS_CCODES, { 0, 0, rm8_i8, 0, 0, rm8_i8_modrm, 0, 1 }, #opname "8AI", "[!0r+!1r<<!2d+!3d],!4r" }, \
+{ kX86 ## opname ## 8TI, kThreadImm,is_store | IS_BINARY_OP | SETS_CCODES, { THREAD_PREFIX, 0, rm8_i8, 0, 0, rm8_i8_modrm, 0, 1 }, #opname "8TI", "fs:[!0d],!1r" }, \
\
-{ kX86 ## opname ## 16MR, kMemReg, IS_STORE | IS_TERTIARY_OP | SETS_CCODES, { 0x66, 0, rm32_r32, 0, 0, 0, 0, 0 }, #opname "16MR", "[!0r+!1d],!2r" }, \
-{ kX86 ## opname ## 16AR, kArrayReg, IS_STORE | IS_QUIN_OP | SETS_CCODES, { 0x66, 0, rm32_r32, 0, 0, 0, 0, 0 }, #opname "16AR", "[!0r+!1r<<!2d+!3d],!4r" }, \
-{ kX86 ## opname ## 16TR, kThreadReg,IS_STORE | IS_BINARY_OP | SETS_CCODES, { THREAD_PREFIX, 0x66, rm32_r32, 0, 0, 0, 0, 0 }, #opname "16TR", "fs:[!0d],!1r" }, \
+{ kX86 ## opname ## 16MR, kMemReg, is_store | IS_TERTIARY_OP | SETS_CCODES, { 0x66, 0, rm32_r32, 0, 0, 0, 0, 0 }, #opname "16MR", "[!0r+!1d],!2r" }, \
+{ kX86 ## opname ## 16AR, kArrayReg, is_store | IS_QUIN_OP | SETS_CCODES, { 0x66, 0, rm32_r32, 0, 0, 0, 0, 0 }, #opname "16AR", "[!0r+!1r<<!2d+!3d],!4r" }, \
+{ kX86 ## opname ## 16TR, kThreadReg,is_store | IS_BINARY_OP | SETS_CCODES, { THREAD_PREFIX, 0x66, rm32_r32, 0, 0, 0, 0, 0 }, #opname "16TR", "fs:[!0d],!1r" }, \
{ kX86 ## opname ## 16RR, kRegReg, IS_BINARY_OP | SETS_CCODES, { 0x66, 0, r32_rm32, 0, 0, 0, 0, 0 }, #opname "16RR", "!0r,!1r" }, \
{ kX86 ## opname ## 16RM, kRegMem, IS_LOAD | IS_TERTIARY_OP | SETS_CCODES, { 0x66, 0, r32_rm32, 0, 0, 0, 0, 0 }, #opname "16RM", "!0r,[!1r+!2d]" }, \
{ kX86 ## opname ## 16RA, kRegArray, IS_LOAD | IS_QUIN_OP | SETS_CCODES, { 0x66, 0, r32_rm32, 0, 0, 0, 0, 0 }, #opname "16RA", "!0r,[!1r+!2r<<!3d+!4d]" }, \
{ kX86 ## opname ## 16RT, kRegThread, IS_LOAD | IS_BINARY_OP | SETS_CCODES, { THREAD_PREFIX, 0x66, r32_rm32, 0, 0, 0, 0, 0 }, #opname "16RT", "!0r,fs:[!1d]" }, \
{ kX86 ## opname ## 16RI, kRegImm, IS_BINARY_OP | SETS_CCODES, { 0x66, 0, rm32_i32, 0, 0, rm32_i32_modrm, ax32_i32, 2 }, #opname "16RI", "!0r,!1d" }, \
-{ kX86 ## opname ## 16MI, kMemImm, IS_STORE | IS_TERTIARY_OP | SETS_CCODES, { 0x66, 0, rm32_i32, 0, 0, rm32_i32_modrm, 0, 2 }, #opname "16MI", "[!0r+!1d],!2d" }, \
-{ kX86 ## opname ## 16AI, kArrayImm, IS_STORE | IS_QUIN_OP | SETS_CCODES, { 0x66, 0, rm32_i32, 0, 0, rm32_i32_modrm, 0, 2 }, #opname "16AI", "[!0r+!1r<<!2d+!3d],!4d" }, \
-{ kX86 ## opname ## 16TI, kThreadImm,IS_STORE | IS_BINARY_OP | SETS_CCODES, { THREAD_PREFIX, 0x66, rm32_i32, 0, 0, rm32_i32_modrm, 0, 2 }, #opname "16TI", "fs:[!0d],!1d" }, \
+{ kX86 ## opname ## 16MI, kMemImm, is_store | IS_TERTIARY_OP | SETS_CCODES, { 0x66, 0, rm32_i32, 0, 0, rm32_i32_modrm, 0, 2 }, #opname "16MI", "[!0r+!1d],!2d" }, \
+{ kX86 ## opname ## 16AI, kArrayImm, is_store | IS_QUIN_OP | SETS_CCODES, { 0x66, 0, rm32_i32, 0, 0, rm32_i32_modrm, 0, 2 }, #opname "16AI", "[!0r+!1r<<!2d+!3d],!4d" }, \
+{ kX86 ## opname ## 16TI, kThreadImm,is_store | IS_BINARY_OP | SETS_CCODES, { THREAD_PREFIX, 0x66, rm32_i32, 0, 0, rm32_i32_modrm, 0, 2 }, #opname "16TI", "fs:[!0d],!1d" }, \
{ kX86 ## opname ## 16RI8, kRegImm, IS_BINARY_OP | SETS_CCODES, { 0x66, 0, rm32_i8, 0, 0, rm32_i8_modrm, 0, 1 }, #opname "16RI8", "!0r,!1d" }, \
-{ kX86 ## opname ## 16MI8, kMemImm, IS_STORE | IS_TERTIARY_OP | SETS_CCODES, { 0x66, 0, rm32_i8, 0, 0, rm32_i8_modrm, 0, 1 }, #opname "16MI8", "[!0r+!1d],!2d" }, \
-{ kX86 ## opname ## 16AI8, kArrayImm, IS_STORE | IS_QUIN_OP | SETS_CCODES, { 0x66, 0, rm32_i8, 0, 0, rm32_i8_modrm, 0, 1 }, #opname "16AI8", "[!0r+!1r<<!2d+!3d],!4d" }, \
-{ kX86 ## opname ## 16TI8, kThreadImm,IS_STORE | IS_BINARY_OP | SETS_CCODES, { THREAD_PREFIX, 0x66, rm32_i8, 0, 0, rm32_i8_modrm, 0, 1 }, #opname "16TI8", "fs:[!0d],!1d" }, \
+{ kX86 ## opname ## 16MI8, kMemImm, is_store | IS_TERTIARY_OP | SETS_CCODES, { 0x66, 0, rm32_i8, 0, 0, rm32_i8_modrm, 0, 1 }, #opname "16MI8", "[!0r+!1d],!2d" }, \
+{ kX86 ## opname ## 16AI8, kArrayImm, is_store | IS_QUIN_OP | SETS_CCODES, { 0x66, 0, rm32_i8, 0, 0, rm32_i8_modrm, 0, 1 }, #opname "16AI8", "[!0r+!1r<<!2d+!3d],!4d" }, \
+{ kX86 ## opname ## 16TI8, kThreadImm,is_store | IS_BINARY_OP | SETS_CCODES, { THREAD_PREFIX, 0x66, rm32_i8, 0, 0, rm32_i8_modrm, 0, 1 }, #opname "16TI8", "fs:[!0d],!1d" }, \
\
-{ kX86 ## opname ## 32MR, kMemReg, IS_STORE | IS_TERTIARY_OP | SETS_CCODES, { 0, 0, rm32_r32, 0, 0, 0, 0, 0 }, #opname "32MR", "[!0r+!1d],!2r" }, \
-{ kX86 ## opname ## 32AR, kArrayReg, IS_STORE | IS_QUIN_OP | SETS_CCODES, { 0, 0, rm32_r32, 0, 0, 0, 0, 0 }, #opname "32AR", "[!0r+!1r<<!2d+!3d],!4r" }, \
-{ kX86 ## opname ## 32TR, kThreadReg,IS_STORE | IS_BINARY_OP | SETS_CCODES, { THREAD_PREFIX, 0, rm32_r32, 0, 0, 0, 0, 0 }, #opname "32TR", "fs:[!0d],!1r" }, \
+{ kX86 ## opname ## 32MR, kMemReg, is_store | IS_TERTIARY_OP | SETS_CCODES, { 0, 0, rm32_r32, 0, 0, 0, 0, 0 }, #opname "32MR", "[!0r+!1d],!2r" }, \
+{ kX86 ## opname ## 32AR, kArrayReg, is_store | IS_QUIN_OP | SETS_CCODES, { 0, 0, rm32_r32, 0, 0, 0, 0, 0 }, #opname "32AR", "[!0r+!1r<<!2d+!3d],!4r" }, \
+{ kX86 ## opname ## 32TR, kThreadReg,is_store | IS_BINARY_OP | SETS_CCODES, { THREAD_PREFIX, 0, rm32_r32, 0, 0, 0, 0, 0 }, #opname "32TR", "fs:[!0d],!1r" }, \
{ kX86 ## opname ## 32RR, kRegReg, IS_BINARY_OP | SETS_CCODES, { 0, 0, r32_rm32, 0, 0, 0, 0, 0 }, #opname "32RR", "!0r,!1r" }, \
{ kX86 ## opname ## 32RM, kRegMem, IS_LOAD | IS_TERTIARY_OP | SETS_CCODES, { 0, 0, r32_rm32, 0, 0, 0, 0, 0 }, #opname "32RM", "!0r,[!1r+!2d]" }, \
{ kX86 ## opname ## 32RA, kRegArray, IS_LOAD | IS_QUIN_OP | SETS_CCODES, { 0, 0, r32_rm32, 0, 0, 0, 0, 0 }, #opname "32RA", "!0r,[!1r+!2r<<!3d+!4d]" }, \
{ kX86 ## opname ## 32RT, kRegThread, IS_LOAD | IS_BINARY_OP | SETS_CCODES, { THREAD_PREFIX, 0, r32_rm32, 0, 0, 0, 0, 0 }, #opname "32RT", "!0r,fs:[!1d]" }, \
{ kX86 ## opname ## 32RI, kRegImm, IS_BINARY_OP | SETS_CCODES, { 0, 0, rm32_i32, 0, 0, rm32_i32_modrm, ax32_i32, 4 }, #opname "32RI", "!0r,!1d" }, \
-{ kX86 ## opname ## 32MI, kMemImm, IS_STORE | IS_TERTIARY_OP | SETS_CCODES, { 0, 0, rm32_i32, 0, 0, rm32_i32_modrm, 0, 4 }, #opname "32MI", "[!0r+!1d],!2r" }, \
-{ kX86 ## opname ## 32AI, kArrayImm, IS_STORE | IS_QUIN_OP | SETS_CCODES, { 0, 0, rm32_i32, 0, 0, rm32_i32_modrm, 0, 4 }, #opname "32AI", "[!0r+!1r<<!2d+!3d],!4d" }, \
-{ kX86 ## opname ## 32TI, kThreadImm,IS_STORE | IS_BINARY_OP | SETS_CCODES, { THREAD_PREFIX, 0, rm32_i32, 0, 0, rm32_i32_modrm, 0, 4 }, #opname "32TI", "fs:[!0d],!1d" }, \
+{ kX86 ## opname ## 32MI, kMemImm, is_store | IS_TERTIARY_OP | SETS_CCODES, { 0, 0, rm32_i32, 0, 0, rm32_i32_modrm, 0, 4 }, #opname "32MI", "[!0r+!1d],!2r" }, \
+{ kX86 ## opname ## 32AI, kArrayImm, is_store | IS_QUIN_OP | SETS_CCODES, { 0, 0, rm32_i32, 0, 0, rm32_i32_modrm, 0, 4 }, #opname "32AI", "[!0r+!1r<<!2d+!3d],!4d" }, \
+{ kX86 ## opname ## 32TI, kThreadImm,is_store | IS_BINARY_OP | SETS_CCODES, { THREAD_PREFIX, 0, rm32_i32, 0, 0, rm32_i32_modrm, 0, 4 }, #opname "32TI", "fs:[!0d],!1d" }, \
{ kX86 ## opname ## 32RI8, kRegImm, IS_BINARY_OP | SETS_CCODES, { 0, 0, rm32_i8, 0, 0, rm32_i8_modrm, 0, 1 }, #opname "32RI8", "!0r,!1d" }, \
-{ kX86 ## opname ## 32MI8, kMemImm, IS_STORE | IS_TERTIARY_OP | SETS_CCODES, { 0, 0, rm32_i8, 0, 0, rm32_i8_modrm, 0, 1 }, #opname "32MI8", "[!0r+!1d],!2d" }, \
-{ kX86 ## opname ## 32AI8, kArrayImm, IS_STORE | IS_QUIN_OP | SETS_CCODES, { 0, 0, rm32_i8, 0, 0, rm32_i8_modrm, 0, 1 }, #opname "32AI8", "[!0r+!1r<<!2d+!3d],!4d" }, \
-{ kX86 ## opname ## 32TI8, kThreadImm,IS_STORE | IS_BINARY_OP | SETS_CCODES, { THREAD_PREFIX, 0, rm32_i8, 0, 0, rm32_i8_modrm, 0, 1 }, #opname "32TI8", "fs:[!0d],!1d" }
+{ kX86 ## opname ## 32MI8, kMemImm, is_store | IS_TERTIARY_OP | SETS_CCODES, { 0, 0, rm32_i8, 0, 0, rm32_i8_modrm, 0, 1 }, #opname "32MI8", "[!0r+!1d],!2d" }, \
+{ kX86 ## opname ## 32AI8, kArrayImm, is_store | IS_QUIN_OP | SETS_CCODES, { 0, 0, rm32_i8, 0, 0, rm32_i8_modrm, 0, 1 }, #opname "32AI8", "[!0r+!1r<<!2d+!3d],!4d" }, \
+{ kX86 ## opname ## 32TI8, kThreadImm,is_store | IS_BINARY_OP | SETS_CCODES, { THREAD_PREFIX, 0, rm32_i8, 0, 0, rm32_i8_modrm, 0, 1 }, #opname "32TI8", "fs:[!0d],!1d" }
-ENCODING_MAP(Add,
+ENCODING_MAP(Add, IS_STORE,
0x00 /* RegMem8/Reg8 */, 0x01 /* RegMem32/Reg32 */,
0x02 /* Reg8/RegMem8 */, 0x03 /* Reg32/RegMem32 */,
0x04 /* Rax8/imm8 opcode */, 0x05 /* Rax32/imm32 */,
0x80, 0x0 /* RegMem8/imm8 */,
0x81, 0x0 /* RegMem32/imm32 */, 0x83, 0x0 /* RegMem32/imm8 */),
-ENCODING_MAP(Or,
+ENCODING_MAP(Or, IS_STORE,
0x08 /* RegMem8/Reg8 */, 0x09 /* RegMem32/Reg32 */,
0x0A /* Reg8/RegMem8 */, 0x0B /* Reg32/RegMem32 */,
0x0C /* Rax8/imm8 opcode */, 0x0D /* Rax32/imm32 */,
0x80, 0x1 /* RegMem8/imm8 */,
0x81, 0x1 /* RegMem32/imm32 */, 0x83, 0x1 /* RegMem32/imm8 */),
-ENCODING_MAP(Adc,
+ENCODING_MAP(Adc, IS_STORE,
0x10 /* RegMem8/Reg8 */, 0x11 /* RegMem32/Reg32 */,
0x12 /* Reg8/RegMem8 */, 0x13 /* Reg32/RegMem32 */,
0x14 /* Rax8/imm8 opcode */, 0x15 /* Rax32/imm32 */,
0x80, 0x2 /* RegMem8/imm8 */,
0x81, 0x2 /* RegMem32/imm32 */, 0x83, 0x2 /* RegMem32/imm8 */),
-ENCODING_MAP(Sbb,
+ENCODING_MAP(Sbb, IS_STORE,
0x18 /* RegMem8/Reg8 */, 0x19 /* RegMem32/Reg32 */,
0x1A /* Reg8/RegMem8 */, 0x1B /* Reg32/RegMem32 */,
0x1C /* Rax8/imm8 opcode */, 0x1D /* Rax32/imm32 */,
0x80, 0x3 /* RegMem8/imm8 */,
0x81, 0x3 /* RegMem32/imm32 */, 0x83, 0x3 /* RegMem32/imm8 */),
-ENCODING_MAP(And,
+ENCODING_MAP(And, IS_STORE,
0x20 /* RegMem8/Reg8 */, 0x21 /* RegMem32/Reg32 */,
0x22 /* Reg8/RegMem8 */, 0x23 /* Reg32/RegMem32 */,
0x24 /* Rax8/imm8 opcode */, 0x25 /* Rax32/imm32 */,
0x80, 0x4 /* RegMem8/imm8 */,
0x81, 0x4 /* RegMem32/imm32 */, 0x83, 0x4 /* RegMem32/imm8 */),
-ENCODING_MAP(Sub,
+ENCODING_MAP(Sub, IS_STORE,
0x28 /* RegMem8/Reg8 */, 0x29 /* RegMem32/Reg32 */,
0x2A /* Reg8/RegMem8 */, 0x2B /* Reg32/RegMem32 */,
0x2C /* Rax8/imm8 opcode */, 0x2D /* Rax32/imm32 */,
0x80, 0x5 /* RegMem8/imm8 */,
0x81, 0x5 /* RegMem32/imm32 */, 0x83, 0x5 /* RegMem32/imm8 */),
-ENCODING_MAP(Xor,
+ENCODING_MAP(Xor, IS_STORE,
0x30 /* RegMem8/Reg8 */, 0x31 /* RegMem32/Reg32 */,
0x32 /* Reg8/RegMem8 */, 0x33 /* Reg32/RegMem32 */,
0x34 /* Rax8/imm8 opcode */, 0x35 /* Rax32/imm32 */,
0x80, 0x6 /* RegMem8/imm8 */,
0x81, 0x6 /* RegMem32/imm32 */, 0x83, 0x6 /* RegMem32/imm8 */),
-ENCODING_MAP(Cmp,
+ENCODING_MAP(Cmp, IS_LOAD,
0x38 /* RegMem8/Reg8 */, 0x39 /* RegMem32/Reg32 */,
0x3A /* Reg8/RegMem8 */, 0x3B /* Reg32/RegMem32 */,
0x3C /* Rax8/imm8 opcode */, 0x3D /* Rax32/imm32 */,
@@ -283,8 +283,8 @@
EXT_0F_ENCODING_MAP(Movsx16, 0x00, 0xBF),
#undef EXT_0F_ENCODING_MAP
- { kX86Jcc, kJcc, IS_BINARY_OP | IS_BRANCH | NEEDS_FIXUP, { 0, 0, 0x70, 0, 0, 0, 0, 0 }, "Jcc", "!1c" },
- { kX86Jmp, kJmp, IS_UNARY_OP | IS_BRANCH | NEEDS_FIXUP, { 0, 0, 0xE9, 0, 0, 0, 0, 0 }, "Jmp", "" },
+ { kX86Jcc, kJcc, IS_BINARY_OP | IS_BRANCH | NEEDS_FIXUP, { 0, 0, 0x70, 0, 0, 0, 0, 0 }, "Jcc", "!1c !0t" },
+ { kX86Jmp, kJmp, IS_UNARY_OP | IS_BRANCH | NEEDS_FIXUP, { 0, 0, 0xE9, 0, 0, 0, 0, 0 }, "Jmp", "!0t" },
{ kX86CallR, kCall, IS_UNARY_OP | IS_BRANCH, { 0, 0, 0xE8, 0, 0, 0, 0, 0 }, "CallR", "!0r" },
{ kX86CallM, kCall, IS_BINARY_OP | IS_BRANCH | IS_LOAD, { 0, 0, 0xFF, 0, 0, 2, 0, 0 }, "CallM", "[!0r+!1d]" },
{ kX86CallA, kCall, IS_QUAD_OP | IS_BRANCH | IS_LOAD, { 0, 0, 0xFF, 0, 0, 2, 0, 0 }, "CallA", "[!0r+!1r<<!2d+!3d]" },
@@ -357,7 +357,7 @@
case kRegArray: // lir operands - 0: reg, 1: base, 2: index, 3: scale, 4: disp
return computeSize(entry, lir->operands[4], true);
case kRegThread: // lir operands - 0: reg, 1: disp
- return computeSize(entry, lir->operands[1], false);
+ return computeSize(entry, 0x12345678, false); // displacement size is always 32bit
case kRegImm: { // lir operands - 0: reg, 1: immediate
int reg = lir->operands[0];
// AX opcodes don't require the modrm byte.
@@ -369,7 +369,7 @@
case kArrayImm: // lir operands - 0: base, 1: index, 2: scale, 3: disp 4: immediate
return computeSize(entry, lir->operands[3], true);
case kThreadImm: // lir operands - 0: disp, 1: imm
- return computeSize(entry, lir->operands[0], false);
+ return computeSize(entry, 0x12345678, false); // displacement size is always 32bit
case kRegRegImm: // lir operands - 0: reg, 1: reg, 2: imm
return computeSize(entry, 0, false);
case kRegMemImm: // lir operands - 0: reg, 1: base, 2: disp, 3: imm
@@ -415,7 +415,7 @@
case kX86CallA: // lir operands - 0: base, 1: index, 2: scale, 3: disp
return computeSize(entry, lir->operands[3], true);
case kX86CallT: // lir operands - 0: disp
- return computeSize(entry, lir->operands[0], true);
+ return computeSize(entry, 0x12345678, false); // displacement size is always 32bit
default:
break;
}
@@ -586,6 +586,40 @@
DCHECK_EQ(0, entry->skeleton.immediate_bytes);
}
+static void emitRegThread(CompilationUnit* cUnit, const X86EncodingMap* entry,
+ uint8_t reg, int disp) {
+ DCHECK_NE(entry->skeleton.prefix1, 0);
+ cUnit->codeBuffer.push_back(entry->skeleton.prefix1);
+ if (entry->skeleton.prefix2 != 0) {
+ cUnit->codeBuffer.push_back(entry->skeleton.prefix2);
+ }
+ cUnit->codeBuffer.push_back(entry->skeleton.opcode);
+ if (entry->skeleton.opcode == 0x0F) {
+ cUnit->codeBuffer.push_back(entry->skeleton.extra_opcode1);
+ if (entry->skeleton.extra_opcode1 == 0x38 || entry->skeleton.extra_opcode2 == 0x3A) {
+ cUnit->codeBuffer.push_back(entry->skeleton.extra_opcode2);
+ } else {
+ DCHECK_EQ(0, entry->skeleton.extra_opcode2);
+ }
+ } else {
+ DCHECK_EQ(0, entry->skeleton.extra_opcode1);
+ DCHECK_EQ(0, entry->skeleton.extra_opcode2);
+ }
+ if (FPREG(reg)) {
+ reg = reg & FP_REG_MASK;
+ }
+ DCHECK_LT(reg, 8);
+ uint8_t modrm = (0 << 6) | (reg << 3) | rBP;
+ cUnit->codeBuffer.push_back(modrm);
+ cUnit->codeBuffer.push_back(disp & 0xFF);
+ cUnit->codeBuffer.push_back((disp >> 8) & 0xFF);
+ cUnit->codeBuffer.push_back((disp >> 16) & 0xFF);
+ cUnit->codeBuffer.push_back((disp >> 24) & 0xFF);
+ DCHECK_EQ(0, entry->skeleton.modrm_opcode);
+ DCHECK_EQ(0, entry->skeleton.ax_opcode);
+ DCHECK_EQ(0, entry->skeleton.immediate_bytes);
+}
+
static void emitRegReg(CompilationUnit* cUnit, const X86EncodingMap* entry,
uint8_t reg1, uint8_t reg2) {
if (entry->skeleton.prefix1 != 0) {
@@ -674,8 +708,160 @@
}
}
+static void emitThreadImm(CompilationUnit* cUnit, const X86EncodingMap* entry,
+ int disp, int imm) {
+ if (entry->skeleton.prefix1 != 0) {
+ cUnit->codeBuffer.push_back(entry->skeleton.prefix1);
+ if (entry->skeleton.prefix2 != 0) {
+ cUnit->codeBuffer.push_back(entry->skeleton.prefix2);
+ }
+ } else {
+ DCHECK_EQ(0, entry->skeleton.prefix2);
+ }
+ cUnit->codeBuffer.push_back(entry->skeleton.opcode);
+ if (entry->skeleton.opcode == 0x0F) {
+ cUnit->codeBuffer.push_back(entry->skeleton.extra_opcode1);
+ if (entry->skeleton.extra_opcode1 == 0x38 || entry->skeleton.extra_opcode2 == 0x3A) {
+ cUnit->codeBuffer.push_back(entry->skeleton.extra_opcode2);
+ } else {
+ DCHECK_EQ(0, entry->skeleton.extra_opcode2);
+ }
+ } else {
+ DCHECK_EQ(0, entry->skeleton.extra_opcode1);
+ DCHECK_EQ(0, entry->skeleton.extra_opcode2);
+ }
+ uint8_t modrm = (0 << 6) | (entry->skeleton.modrm_opcode << 3) | rBP;
+ cUnit->codeBuffer.push_back(modrm);
+ cUnit->codeBuffer.push_back(disp & 0xFF);
+ cUnit->codeBuffer.push_back((disp >> 8) & 0xFF);
+ cUnit->codeBuffer.push_back((disp >> 16) & 0xFF);
+ cUnit->codeBuffer.push_back((disp >> 24) & 0xFF);
+ switch (entry->skeleton.immediate_bytes) {
+ case 1:
+ DCHECK(IS_SIMM8(imm));
+ cUnit->codeBuffer.push_back(imm & 0xFF);
+ break;
+ case 2:
+ DCHECK(IS_SIMM16(imm));
+ cUnit->codeBuffer.push_back(imm & 0xFF);
+ cUnit->codeBuffer.push_back((imm >> 8) & 0xFF);
+ break;
+ case 4:
+ cUnit->codeBuffer.push_back(imm & 0xFF);
+ cUnit->codeBuffer.push_back((imm >> 8) & 0xFF);
+ cUnit->codeBuffer.push_back((imm >> 16) & 0xFF);
+ cUnit->codeBuffer.push_back((imm >> 24) & 0xFF);
+ break;
+ default:
+ LOG(FATAL) << "Unexpected immediate bytes (" << entry->skeleton.immediate_bytes
+ << ") for instruction: " << entry->name;
+ break;
+ }
+ DCHECK_EQ(entry->skeleton.ax_opcode, 0);
+}
+
+static void emitMovRegImm(CompilationUnit* cUnit, const X86EncodingMap* entry,
+ uint8_t reg, int imm) {
+ DCHECK_LT(reg, 8);
+ cUnit->codeBuffer.push_back(0xB8 + reg);
+ cUnit->codeBuffer.push_back(imm & 0xFF);
+ cUnit->codeBuffer.push_back((imm >> 8) & 0xFF);
+ cUnit->codeBuffer.push_back((imm >> 16) & 0xFF);
+ cUnit->codeBuffer.push_back((imm >> 24) & 0xFF);
+}
+
+static void emitJmp(CompilationUnit* cUnit, const X86EncodingMap* entry, int rel) {
+ if (IS_SIMM8(rel)) {
+ cUnit->codeBuffer.push_back(0xEB);
+ cUnit->codeBuffer.push_back(rel & 0xFF);
+ } else {
+ cUnit->codeBuffer.push_back(0xE9);
+ cUnit->codeBuffer.push_back(rel & 0xFF);
+ cUnit->codeBuffer.push_back((rel >> 8) & 0xFF);
+ cUnit->codeBuffer.push_back((rel >> 16) & 0xFF);
+ cUnit->codeBuffer.push_back((rel >> 24) & 0xFF);
+ }
+}
+
+static void emitJcc(CompilationUnit* cUnit, const X86EncodingMap* entry,
+ int rel, uint8_t cc) {
+ DCHECK_LT(cc, 16);
+ if (IS_SIMM8(rel)) {
+ cUnit->codeBuffer.push_back(0x70 | cc);
+ cUnit->codeBuffer.push_back(rel & 0xFF);
+ } else {
+ cUnit->codeBuffer.push_back(0x0F);
+ cUnit->codeBuffer.push_back(0x80 | cc);
+ cUnit->codeBuffer.push_back(rel & 0xFF);
+ cUnit->codeBuffer.push_back((rel >> 8) & 0xFF);
+ cUnit->codeBuffer.push_back((rel >> 16) & 0xFF);
+ cUnit->codeBuffer.push_back((rel >> 24) & 0xFF);
+ }
+}
+
+static void emitCallMem(CompilationUnit* cUnit, const X86EncodingMap* entry,
+ uint8_t base, int disp) {
+ if (entry->skeleton.prefix1 != 0) {
+ cUnit->codeBuffer.push_back(entry->skeleton.prefix1);
+ if (entry->skeleton.prefix2 != 0) {
+ cUnit->codeBuffer.push_back(entry->skeleton.prefix2);
+ }
+ } else {
+ DCHECK_EQ(0, entry->skeleton.prefix2);
+ }
+ cUnit->codeBuffer.push_back(entry->skeleton.opcode);
+ if (entry->skeleton.opcode == 0x0F) {
+ cUnit->codeBuffer.push_back(entry->skeleton.extra_opcode1);
+ if (entry->skeleton.extra_opcode1 == 0x38 || entry->skeleton.extra_opcode2 == 0x3A) {
+ cUnit->codeBuffer.push_back(entry->skeleton.extra_opcode2);
+ } else {
+ DCHECK_EQ(0, entry->skeleton.extra_opcode2);
+ }
+ } else {
+ DCHECK_EQ(0, entry->skeleton.extra_opcode1);
+ DCHECK_EQ(0, entry->skeleton.extra_opcode2);
+ }
+ uint8_t modrm = (modrmForDisp(disp) << 6) | (entry->skeleton.modrm_opcode << 3) | base;
+ cUnit->codeBuffer.push_back(modrm);
+ if (base == rSP) {
+ // Special SIB for SP base
+ cUnit->codeBuffer.push_back(0 << 6 | (rSP << 3) | rSP);
+ }
+ emitDisp(cUnit, disp);
+ DCHECK_EQ(0, entry->skeleton.ax_opcode);
+ DCHECK_EQ(0, entry->skeleton.immediate_bytes);
+}
+
+static void emitCallThread(CompilationUnit* cUnit, const X86EncodingMap* entry, int disp) {
+ DCHECK_NE(entry->skeleton.prefix1, 0);
+ cUnit->codeBuffer.push_back(entry->skeleton.prefix1);
+ if (entry->skeleton.prefix2 != 0) {
+ cUnit->codeBuffer.push_back(entry->skeleton.prefix2);
+ }
+ cUnit->codeBuffer.push_back(entry->skeleton.opcode);
+ if (entry->skeleton.opcode == 0x0F) {
+ cUnit->codeBuffer.push_back(entry->skeleton.extra_opcode1);
+ if (entry->skeleton.extra_opcode1 == 0x38 || entry->skeleton.extra_opcode2 == 0x3A) {
+ cUnit->codeBuffer.push_back(entry->skeleton.extra_opcode2);
+ } else {
+ DCHECK_EQ(0, entry->skeleton.extra_opcode2);
+ }
+ } else {
+ DCHECK_EQ(0, entry->skeleton.extra_opcode1);
+ DCHECK_EQ(0, entry->skeleton.extra_opcode2);
+ }
+ uint8_t modrm = (0 << 6) | (entry->skeleton.modrm_opcode << 3) | rBP;
+ cUnit->codeBuffer.push_back(modrm);
+ cUnit->codeBuffer.push_back(disp & 0xFF);
+ cUnit->codeBuffer.push_back((disp >> 8) & 0xFF);
+ cUnit->codeBuffer.push_back((disp >> 16) & 0xFF);
+ cUnit->codeBuffer.push_back((disp >> 24) & 0xFF);
+ DCHECK_EQ(0, entry->skeleton.ax_opcode);
+ DCHECK_EQ(0, entry->skeleton.immediate_bytes);
+}
+
void emitUnimplemented(CompilationUnit* cUnit, const X86EncodingMap* entry, LIR* lir) {
- UNIMPLEMENTED(WARNING) << "Unimplemented encoding for: " << entry->name;
+ UNIMPLEMENTED(WARNING) << "encoding for: " << entry->name;
for (int i = 0; i < oatGetInsnSize(lir); ++i) {
cUnit->codeBuffer.push_back(0xCC); // push breakpoint instruction - int 3
}
@@ -687,8 +873,7 @@
* instruction. In those cases we will try to substitute a new code
* sequence or request that the trace be shortened and retried.
*/
-AssemblerStatus oatAssembleInstructions(CompilationUnit *cUnit,
- intptr_t startAddr) {
+AssemblerStatus oatAssembleInstructions(CompilationUnit *cUnit, intptr_t startAddr) {
LIR *lir;
AssemblerStatus res = kSuccess; // Assume success
@@ -703,7 +888,50 @@
}
if (lir->flags.pcRelFixup) {
- UNIMPLEMENTED(WARNING) << "PC relative fix up";
+ switch (lir->opcode) {
+ case kX86Jcc: {
+ LIR *targetLIR = lir->target;
+ DCHECK(targetLIR != NULL);
+ int delta = 0;
+ intptr_t pc;
+ if (IS_SIMM8(lir->operands[0])) {
+ pc = lir->offset + 2 /* opcode + rel8 */;
+ } else {
+ pc = lir->offset + 6 /* 2 byte opcode + rel32 */;
+ }
+ intptr_t target = targetLIR->offset;
+ delta = target - pc;
+ if (IS_SIMM8(delta) != IS_SIMM8(lir->operands[0])) {
+ res = kRetryAll;
+ }
+ lir->operands[0] = delta;
+ break;
+ }
+ case kX86Jmp: {
+ LIR *targetLIR = lir->target;
+ DCHECK(targetLIR != NULL);
+ int delta = 0;
+ intptr_t pc;
+ if (IS_SIMM8(lir->operands[0])) {
+ pc = lir->offset + 2 /* opcode + rel8 */;
+ } else {
+ pc = lir->offset + 5 /* opcode + rel32 */;
+ }
+ intptr_t target = targetLIR->offset;
+ delta = target - pc;
+ if (!(cUnit->disableOpt & (1 << kSafeOptimizations)) && lir->operands[0] == 0) {
+ // Useless branch
+ lir->flags.isNop = true;
+ res = kRetryAll;
+ } else if (IS_SIMM8(delta) != IS_SIMM8(lir->operands[0])) {
+ res = kRetryAll;
+ }
+ lir->operands[0] = delta;
+ break;
+ }
+ default:
+ break;
+ }
}
/*
@@ -746,18 +974,48 @@
emitRegArray(cUnit, entry, lir->operands[0], lir->operands[1], lir->operands[2],
lir->operands[3], lir->operands[4]);
break;
+ case kRegThread: // lir operands - 0: reg, 1: disp
+ emitRegThread(cUnit, entry, lir->operands[0], lir->operands[1]);
+ break;
case kRegReg: // lir operands - 0: reg1, 1: reg2
emitRegReg(cUnit, entry, lir->operands[0], lir->operands[1]);
break;
case kRegImm: // lir operands - 0: reg, 1: immediate
emitRegImm(cUnit, entry, lir->operands[0], lir->operands[1]);
break;
+ case kThreadImm: // lir operands - 0: disp, 1: immediate
+ emitThreadImm(cUnit, entry, lir->operands[0], lir->operands[1]);
+ break;
+ case kMovRegImm: // lir operands - 0: reg, 1: immediate
+ emitMovRegImm(cUnit, entry, lir->operands[0], lir->operands[1]);
+ break;
+ case kJmp: // lir operands - 0: rel
+ emitJmp(cUnit, entry, lir->operands[0]);
+ break;
+ case kJcc: // lir operands - 0: rel, 1: CC, target assigned
+ emitJcc(cUnit, entry, lir->operands[0], lir->operands[1]);
+ break;
+ case kCall:
+ switch(entry->opcode) {
+ case kX86CallM: // lir operands - 0: base, 1: disp
+ emitCallMem(cUnit, entry, lir->operands[0], lir->operands[1]);
+ break;
+ case kX86CallT: // lir operands - 0: disp
+ emitCallThread(cUnit, entry, lir->operands[0]);
+ break;
+ default:
+ emitUnimplemented(cUnit, entry, lir);
+ break;
+ }
+ break;
default:
emitUnimplemented(cUnit, entry, lir);
break;
}
CHECK_EQ(static_cast<size_t>(oatGetInsnSize(lir)),
- cUnit->codeBuffer.size() - starting_cbuf_size);
+ cUnit->codeBuffer.size() - starting_cbuf_size)
+ << "Instruction size mismatch for entry: " << EncodingMap[lir->opcode].name;
+
}
return res;
}
diff --git a/src/compiler_test.cc b/src/compiler_test.cc
index 272f838..d59576d 100644
--- a/src/compiler_test.cc
+++ b/src/compiler_test.cc
@@ -126,7 +126,6 @@
}
TEST_F(CompilerTest, AbstractMethodErrorStub) {
-#if defined(__arm__)
CompileVirtualMethod(NULL, "java.lang.Class", "isFinalizable", "()Z");
CompileDirectMethod(NULL, "java.lang.Object", "<init>", "()V");
@@ -146,7 +145,6 @@
EXPECT_TRUE(Thread::Current()->IsExceptionPending());
EXPECT_TRUE(Thread::Current()->GetException()->InstanceOf(jlame));
Thread::Current()->ClearException();
-#endif // __arm__
}
// TODO: need check-cast test (when stub complete & we can throw/catch
diff --git a/src/object.cc b/src/object.cc
index 59fa28b..979c79a 100644
--- a/src/object.cc
+++ b/src/object.cc
@@ -567,10 +567,6 @@
const Method::InvokeStub* stub = GetInvokeStub();
bool have_executable_code = (GetCode() != NULL);
-#if !defined(__arm__)
- // Currently we can only compile non-native methods for ARM.
- have_executable_code = IsNative();
-#endif
if (Runtime::Current()->IsStarted() && have_executable_code && stub != NULL) {
bool log = false;
diff --git a/src/stub_x86.cc b/src/stub_x86.cc
index c330f78..1820f5f 100644
--- a/src/stub_x86.cc
+++ b/src/stub_x86.cc
@@ -45,17 +45,24 @@
ByteArray* CreateAbstractMethodErrorStub() {
UniquePtr<X86Assembler> assembler(static_cast<X86Assembler*>(Assembler::Create(kX86)));
- // Pad stack to ensure 16-byte alignment
+ // return address
+ __ pushl(EDI);
+ __ pushl(ESI);
+ __ pushl(EBP);
+ __ pushl(EBX);
__ pushl(Immediate(0));
+ __ pushl(Immediate(0));
+ __ pushl(Immediate(0)); // <-- callee save Method* to go here
+ __ movl(ECX, ESP); // save ESP
+ __ pushl(Immediate(0)); // align frame
+ __ pushl(ECX); // pass ESP for Method*
__ fs()->pushl(Address::Absolute(Thread::SelfOffset())); // Thread*
- __ pushl(EAX); // Method*
+ __ pushl(EAX); // pass Method*
- // Call to throw AbstractMethodError
+ // Call to throw AbstractMethodError.
__ Call(ThreadOffset(OFFSETOF_MEMBER(Thread, pThrowAbstractMethodErrorFromCode)),
X86ManagedRegister::FromCpuRegister(ECX));
-
- // Because the call above never returns, we do not need to do ESP+=16 here.
-
+ // Call never returns.
__ int3();
assembler->EmitSlowPaths();
diff --git a/src/thread.cc b/src/thread.cc
index d9de1cb..e1a8946 100644
--- a/src/thread.cc
+++ b/src/thread.cc
@@ -166,6 +166,74 @@
pUnlockObjectFromCode = art_unlock_object_from_code;
pUpdateDebuggerFromCode = NULL; // To enable, set to art_update_debugger
#endif
+#if defined(__i386__)
+ pShlLong = NULL;
+ pShrLong = NULL;
+ pUshrLong = NULL;
+ pIdiv = NULL;
+ pIdivmod = NULL;
+ pI2f = NULL;
+ pF2iz = NULL;
+ pD2f = NULL;
+ pF2d = NULL;
+ pD2iz = NULL;
+ pL2f = NULL;
+ pL2d = NULL;
+ pFadd = NULL;
+ pFsub = NULL;
+ pFdiv = NULL;
+ pFmul = NULL;
+ pFmodf = NULL;
+ pDadd = NULL;
+ pDsub = NULL;
+ pDdiv = NULL;
+ pDmul = NULL;
+ pFmod = NULL;
+ pLdivmod = NULL;
+ pLmul = NULL;
+ pAllocArrayFromCode = NULL;
+ pAllocArrayFromCodeWithAccessCheck = NULL;
+ pAllocObjectFromCode = NULL;
+ pAllocObjectFromCodeWithAccessCheck = NULL;
+ pCanPutArrayElementFromCode = NULL;
+ pCheckAndAllocArrayFromCode = NULL;
+ pCheckAndAllocArrayFromCodeWithAccessCheck = NULL;
+ pCheckCastFromCode = NULL;
+ pGet32Instance = NULL;
+ pGet64Instance = NULL;
+ pGetObjInstance = NULL;
+ pGet32Static = NULL;
+ pGet64Static = NULL;
+ pGetObjStatic = NULL;
+ pHandleFillArrayDataFromCode = NULL;
+ pInitializeStaticStorage = NULL;
+ pInitializeTypeFromCode = NULL;
+ pInitializeTypeAndVerifyAccessFromCode = NULL;
+ pInvokeDirectTrampolineWithAccessCheck = NULL;
+ pInvokeInterfaceTrampoline = NULL;
+ pInvokeInterfaceTrampolineWithAccessCheck = NULL;
+ pInvokeStaticTrampolineWithAccessCheck = NULL;
+ pInvokeSuperTrampolineWithAccessCheck = NULL;
+ pInvokeVirtualTrampolineWithAccessCheck = NULL;
+ pLockObjectFromCode = NULL;
+ pResolveStringFromCode = NULL;
+ pSet32Instance = NULL;
+ pSet64Instance = NULL;
+ pSetObjInstance = NULL;
+ pSet32Static = NULL;
+ pSet64Static = NULL;
+ pSetObjStatic = NULL;
+ pTestSuspendFromCode = NULL;
+ pThrowArrayBoundsFromCode = NULL;
+ pThrowDivZeroFromCode = NULL;
+ pThrowNegArraySizeFromCode = NULL;
+ pThrowNoSuchMethodFromCode = NULL;
+ pThrowNullPointerFromCode = NULL;
+ pThrowStackOverflowFromCode = NULL;
+ pThrowVerificationErrorFromCode = NULL;
+ pUnlockObjectFromCode = NULL;
+ pUpdateDebuggerFromCode = NULL; // To enable, set to art_update_debugger
+#endif
pF2l = F2L;
pD2l = D2L;
pMemcpy = memcpy;