64-bit temp register support.
Add a 64-bit temp register allocation path. The recent physical
register handling rework supports multiple views of the same
physical register (or, such as for Arm's float/double regs,
different parts of the same physical register).
This CL adds a 64-bit core register view for 64-bit targets. In
short, each core register will have a 64-bit name, and a 32-bit
name. The different views will be kept in separate register pools,
but aliasing will be tracked. The core temp register allocation
routines will be largely identical - except for 32-bit targets,
which will continue to use pairs of 32-bit core registers for holding
long values.
Change-Id: I8f118e845eac7903ad8b6dcec1952f185023c053
diff --git a/compiler/dex/quick/arm/target_arm.cc b/compiler/dex/quick/arm/target_arm.cc
index f7a7fe8..1520c52 100644
--- a/compiler/dex/quick/arm/target_arm.cc
+++ b/compiler/dex/quick/arm/target_arm.cc
@@ -46,6 +46,7 @@
static const RegStorage dp_temps_arr[] =
{rs_dr0, rs_dr1, rs_dr2, rs_dr3, rs_dr4, rs_dr5, rs_dr6, rs_dr7};
+static const std::vector<RegStorage> empty_pool;
static const std::vector<RegStorage> core_regs(core_regs_arr,
core_regs_arr + sizeof(core_regs_arr) / sizeof(core_regs_arr[0]));
static const std::vector<RegStorage> sp_regs(sp_regs_arr,
@@ -554,26 +555,11 @@
return new ArmMir2Lir(cu, mir_graph, arena);
}
-// Alloc a pair of core registers, or a double.
-RegStorage ArmMir2Lir::AllocTypedTempWide(bool fp_hint, int reg_class) {
- if (((reg_class == kAnyReg) && fp_hint) || (reg_class == kFPReg)) {
- return AllocTempDouble();
- } else {
- RegStorage low_reg = AllocTemp();
- RegStorage high_reg = AllocTemp();
- return RegStorage::MakeRegPair(low_reg, high_reg);
- }
-}
-
-RegStorage ArmMir2Lir::AllocTypedTemp(bool fp_hint, int reg_class) {
- if (((reg_class == kAnyReg) && fp_hint) || (reg_class == kFPReg))
- return AllocTempSingle();
- return AllocTemp();
-}
-
void ArmMir2Lir::CompilerInitializeRegAlloc() {
- reg_pool_ = new (arena_) RegisterPool(this, arena_, core_regs, sp_regs, dp_regs, reserved_regs,
- core_temps, sp_temps, dp_temps);
+ reg_pool_ = new (arena_) RegisterPool(this, arena_, core_regs, empty_pool /* core64 */, sp_regs,
+ dp_regs, reserved_regs, empty_pool /* reserved64 */,
+ core_temps, empty_pool /* core64_temps */, sp_temps,
+ dp_temps);
// Target-specific adjustments.