commit a8eef82f394f31272610d7ed80328ee465fa1a0f
author Nicolas Geoffray <ngeoffray@google.com> Fri Jan 16 11:14:27 2015 +0000
committer Nicolas Geoffray <ngeoffray@google.com> Mon Jan 19 09:10:12 2015 +0000
tree 363103fcf07b2b4e6c944b02984d3f345b2949f1
parent c2c7a33a25169cdf19a0dcf45ddb3747055c7296

Do not use STMP, it conflicts with the calling convention.

Hard-float calling convention uses S14 and D7 for argument passing,
so we cannot use them.

Change-Id: I77a2d8c875677640204baebc24355051aa4175fd

compiler/optimizing/code_generator_arm.cc

diff --git a/compiler/optimizing/code_generator_arm.cc b/compiler/optimizing/code_generator_arm.cc
index 5b2db13..7ece4b2e 100644
--- a/compiler/optimizing/code_generator_arm.cc
+++ b/compiler/optimizing/code_generator_arm.cc
@@ -49,9 +49,6 @@
 static constexpr size_t kRuntimeParameterFpuRegistersLength =
     arraysize(kRuntimeParameterFpuRegisters);
 
-static constexpr DRegister DTMP = D7;
-static constexpr SRegister STMP = S14;
-
 class InvokeRuntimeCallingConvention : public CallingConvention<Register, SRegister> {
  public:
   InvokeRuntimeCallingConvention()
@@ -475,11 +472,6 @@
   blocked_core_registers_[R10] = true;
   blocked_core_registers_[R11] = true;
 
-  // Don't allocate our temporary double register.
-  blocked_fpu_registers_[STMP] = true;
-  blocked_fpu_registers_[STMP + 1] = true;
-  DCHECK_EQ(FromLowSToD(STMP), DTMP);
-
   blocked_fpu_registers_[S16] = true;
   blocked_fpu_registers_[S17] = true;
   blocked_fpu_registers_[S18] = true;
@@ -3374,9 +3366,9 @@
   } else if (source.IsStackSlot() && destination.IsStackSlot()) {
     Exchange(source.GetStackIndex(), destination.GetStackIndex());
   } else if (source.IsFpuRegister() && destination.IsFpuRegister()) {
-    __ vmovs(STMP, source.AsFpuRegister<SRegister>());
+    __ vmovrs(IP, source.AsFpuRegister<SRegister>());
     __ vmovs(source.AsFpuRegister<SRegister>(), destination.AsFpuRegister<SRegister>());
-    __ vmovs(destination.AsFpuRegister<SRegister>(), STMP);
+    __ vmovsr(destination.AsFpuRegister<SRegister>(), IP);
   } else if (source.IsFpuRegister() || destination.IsFpuRegister()) {
     SRegister reg = source.IsFpuRegister() ? source.AsFpuRegister<SRegister>()
                                            : destination.AsFpuRegister<SRegister>();
@@ -3384,13 +3376,10 @@
         ? destination.GetStackIndex()
         : source.GetStackIndex();
 
-    __ vmovs(STMP, reg);
-    __ LoadSFromOffset(reg, SP, mem);
-    __ StoreSToOffset(STMP, SP, mem);
+    __ vmovrs(IP, reg);
+    __ LoadFromOffset(kLoadWord, IP, SP, mem);
+    __ StoreToOffset(kStoreWord, IP, SP, mem);
   } else if (source.IsDoubleStackSlot() && destination.IsDoubleStackSlot()) {
-    // TODO: We could use DTMP and ask for a pair scratch register (float or core).
-    // This would save four instructions if two scratch registers are available, and
-    // two instructions if not.
     Exchange(source.GetStackIndex(), destination.GetStackIndex());
     Exchange(source.GetHighStackIndex(kArmWordSize), destination.GetHighStackIndex(kArmWordSize));
   } else {