MIPS32: Allow some patched instructions in delay slots
Test: test-art-host-gtest
Test: booted MIPS64 (with 2nd arch MIPS32R6) in QEMU
Test: test-art-target-gtest32
Test: testrunner.py --target --optimizing --32
Test: same tests as above on CI20
Test: booted MIPS32R2 in QEMU
Change-Id: I7e1ba59993008014d0115ae20c56e0a71fef0fb0
diff --git a/compiler/optimizing/code_generator_mips.cc b/compiler/optimizing/code_generator_mips.cc
index 2e78af5..51f5b96 100644
--- a/compiler/optimizing/code_generator_mips.cc
+++ b/compiler/optimizing/code_generator_mips.cc
@@ -267,13 +267,10 @@
DCHECK(bss_info_high_);
CodeGeneratorMIPS::PcRelativePatchInfo* info_low =
mips_codegen->NewTypeBssEntryPatch(cls_->GetDexFile(), type_index, bss_info_high_);
- bool reordering = __ SetReorder(false);
- __ Bind(&info_low->label);
- __ StoreToOffset(kStoreWord,
- calling_convention.GetRegisterAt(0),
- entry_address,
- /* placeholder */ 0x5678);
- __ SetReorder(reordering);
+ __ Sw(calling_convention.GetRegisterAt(0),
+ entry_address,
+ /* placeholder */ 0x5678,
+ &info_low->label);
}
// Move the class to the desired location.
@@ -296,10 +293,8 @@
mips_codegen->NewTypeBssEntryPatch(cls_->GetDexFile(), type_index);
CodeGeneratorMIPS::PcRelativePatchInfo* info_low =
mips_codegen->NewTypeBssEntryPatch(cls_->GetDexFile(), type_index, info_high);
- bool reordering = __ SetReorder(false);
- mips_codegen->EmitPcRelativeAddressPlaceholderHigh(info_high, TMP, base, info_low);
- __ StoreToOffset(kStoreWord, out.AsRegister<Register>(), TMP, /* placeholder */ 0x5678);
- __ SetReorder(reordering);
+ mips_codegen->EmitPcRelativeAddressPlaceholderHigh(info_high, TMP, base);
+ __ Sw(out.AsRegister<Register>(), TMP, /* placeholder */ 0x5678, &info_low->label);
}
__ B(GetExitLabel());
}
@@ -366,13 +361,10 @@
DCHECK(bss_info_high_);
CodeGeneratorMIPS::PcRelativePatchInfo* info_low =
mips_codegen->NewPcRelativeStringPatch(load->GetDexFile(), string_index, bss_info_high_);
- bool reordering = __ SetReorder(false);
- __ Bind(&info_low->label);
- __ StoreToOffset(kStoreWord,
- calling_convention.GetRegisterAt(0),
- entry_address,
- /* placeholder */ 0x5678);
- __ SetReorder(reordering);
+ __ Sw(calling_convention.GetRegisterAt(0),
+ entry_address,
+ /* placeholder */ 0x5678,
+ &info_low->label);
}
Primitive::Type type = instruction_->GetType();
@@ -391,10 +383,8 @@
mips_codegen->NewPcRelativeStringPatch(load->GetDexFile(), string_index);
CodeGeneratorMIPS::PcRelativePatchInfo* info_low =
mips_codegen->NewPcRelativeStringPatch(load->GetDexFile(), string_index, info_high);
- bool reordering = __ SetReorder(false);
- mips_codegen->EmitPcRelativeAddressPlaceholderHigh(info_high, TMP, base, info_low);
- __ StoreToOffset(kStoreWord, out, TMP, /* placeholder */ 0x5678);
- __ SetReorder(reordering);
+ mips_codegen->EmitPcRelativeAddressPlaceholderHigh(info_high, TMP, base);
+ __ Sw(out, TMP, /* placeholder */ 0x5678, &info_low->label);
}
__ B(GetExitLabel());
}
@@ -1743,16 +1733,17 @@
void CodeGeneratorMIPS::EmitPcRelativeAddressPlaceholderHigh(PcRelativePatchInfo* info_high,
Register out,
- Register base,
- PcRelativePatchInfo* info_low) {
+ Register base) {
DCHECK(!info_high->patch_info_high);
DCHECK_NE(out, base);
+ bool reordering = __ SetReorder(false);
if (GetInstructionSetFeatures().IsR6()) {
DCHECK_EQ(base, ZERO);
__ Bind(&info_high->label);
__ Bind(&info_high->pc_rel_label);
// Add the high half of a 32-bit offset to PC.
__ Auipc(out, /* placeholder */ 0x1234);
+ __ SetReorder(reordering);
} else {
// If base is ZERO, emit NAL to obtain the actual base.
if (base == ZERO) {
@@ -1766,15 +1757,12 @@
if (base == ZERO) {
__ Bind(&info_high->pc_rel_label);
}
+ __ SetReorder(reordering);
// Add the high half of a 32-bit offset to PC.
__ Addu(out, out, (base == ZERO) ? RA : base);
}
// A following instruction will add the sign-extended low half of the 32-bit
// offset to `out` (e.g. lw, jialc, addiu).
- if (info_low != nullptr) {
- DCHECK_EQ(info_low->patch_info_high, info_high);
- __ Bind(&info_low->label);
- }
}
CodeGeneratorMIPS::JitPatchInfo* CodeGeneratorMIPS::NewJitRootStringPatch(
@@ -7515,11 +7503,9 @@
PcRelativePatchInfo* info_high = NewPcRelativeMethodPatch(invoke->GetTargetMethod());
PcRelativePatchInfo* info_low =
NewPcRelativeMethodPatch(invoke->GetTargetMethod(), info_high);
- bool reordering = __ SetReorder(false);
Register temp_reg = temp.AsRegister<Register>();
- EmitPcRelativeAddressPlaceholderHigh(info_high, TMP, base_reg, info_low);
- __ Addiu(temp_reg, TMP, /* placeholder */ 0x5678);
- __ SetReorder(reordering);
+ EmitPcRelativeAddressPlaceholderHigh(info_high, TMP, base_reg);
+ __ Addiu(temp_reg, TMP, /* placeholder */ 0x5678, &info_low->label);
break;
}
case HInvokeStaticOrDirect::MethodLoadKind::kDirectAddress:
@@ -7531,10 +7517,8 @@
PcRelativePatchInfo* info_low = NewMethodBssEntryPatch(
MethodReference(&GetGraph()->GetDexFile(), invoke->GetDexMethodIndex()), info_high);
Register temp_reg = temp.AsRegister<Register>();
- bool reordering = __ SetReorder(false);
- EmitPcRelativeAddressPlaceholderHigh(info_high, TMP, base_reg, info_low);
- __ Lw(temp_reg, TMP, /* placeholder */ 0x5678);
- __ SetReorder(reordering);
+ EmitPcRelativeAddressPlaceholderHigh(info_high, TMP, base_reg);
+ __ Lw(temp_reg, TMP, /* placeholder */ 0x5678, &info_low->label);
break;
}
case HInvokeStaticOrDirect::MethodLoadKind::kRuntimeCall: {
@@ -7729,13 +7713,10 @@
codegen_->NewPcRelativeTypePatch(cls->GetDexFile(), cls->GetTypeIndex());
CodeGeneratorMIPS::PcRelativePatchInfo* info_low =
codegen_->NewPcRelativeTypePatch(cls->GetDexFile(), cls->GetTypeIndex(), info_high);
- bool reordering = __ SetReorder(false);
codegen_->EmitPcRelativeAddressPlaceholderHigh(info_high,
out,
- base_or_current_method_reg,
- info_low);
- __ Addiu(out, out, /* placeholder */ 0x5678);
- __ SetReorder(reordering);
+ base_or_current_method_reg);
+ __ Addiu(out, out, /* placeholder */ 0x5678, &info_low->label);
break;
}
case HLoadClass::LoadKind::kBootImageAddress: {
@@ -7754,11 +7735,9 @@
codegen_->NewTypeBssEntryPatch(cls->GetDexFile(), cls->GetTypeIndex(), bss_info_high);
constexpr bool non_baker_read_barrier = kUseReadBarrier && !kUseBakerReadBarrier;
Register temp = non_baker_read_barrier ? out : locations->GetTemp(0).AsRegister<Register>();
- bool reordering = __ SetReorder(false);
codegen_->EmitPcRelativeAddressPlaceholderHigh(bss_info_high,
temp,
base_or_current_method_reg);
- __ SetReorder(reordering);
GenerateGcRootFieldLoad(cls,
out_loc,
temp,
@@ -7899,13 +7878,10 @@
codegen_->NewPcRelativeStringPatch(load->GetDexFile(), load->GetStringIndex());
CodeGeneratorMIPS::PcRelativePatchInfo* info_low =
codegen_->NewPcRelativeStringPatch(load->GetDexFile(), load->GetStringIndex(), info_high);
- bool reordering = __ SetReorder(false);
codegen_->EmitPcRelativeAddressPlaceholderHigh(info_high,
out,
- base_or_current_method_reg,
- info_low);
- __ Addiu(out, out, /* placeholder */ 0x5678);
- __ SetReorder(reordering);
+ base_or_current_method_reg);
+ __ Addiu(out, out, /* placeholder */ 0x5678, &info_low->label);
return; // No dex cache slow path.
}
case HLoadString::LoadKind::kBootImageAddress: {
@@ -7925,11 +7901,9 @@
codegen_->NewPcRelativeStringPatch(load->GetDexFile(), load->GetStringIndex(), info_high);
constexpr bool non_baker_read_barrier = kUseReadBarrier && !kUseBakerReadBarrier;
Register temp = non_baker_read_barrier ? out : locations->GetTemp(0).AsRegister<Register>();
- bool reordering = __ SetReorder(false);
codegen_->EmitPcRelativeAddressPlaceholderHigh(info_high,
temp,
base_or_current_method_reg);
- __ SetReorder(reordering);
GenerateGcRootFieldLoad(load,
out_loc,
temp,