commit a61f49539a59b610e557b5513695295639496750
author buzbee <buzbee@google.com> Fri Aug 23 14:27:06 2013 -0700
committer buzbee <buzbee@google.com> Fri Oct 25 07:42:26 2013 -0700
tree f2a52e9e5b3db371cf0407614b51bc27397c39d3
parent 1984152ac92aad244ae15184d12f9ceade686b7b

Add timing logger to Quick compiler

Current Quick compiler breakdown for compiling the boot class path:

MIR2LIR:                    29.674%
MIROpt:SSATransform:        17.656%
MIROpt:BBOpt:               11.508%
BuildMIRGraph:               7.815%
Assemble:                    6.898%
MIROpt:ConstantProp:         5.151%
Cleanup:                     4.916%
MIROpt:NullCheckElimination: 4.085%
RegisterAllocation:          3.972%
GcMap:                       2.359%
Launchpads:                  2.147%
PcMappingTable:              2.145%
MIROpt:CodeLayout:           0.697%
LiteralData:                 0.654%
SpecialMIR2LIR:              0.323%

Change-Id: I9f77e825faf79e6f6b214bb42edcc4b36f55d291

compiler/dex/quick/codegen_util.cc

diff --git a/compiler/dex/quick/codegen_util.cc b/compiler/dex/quick/codegen_util.cc
index 2ce8f58..a6653fa 100644
--- a/compiler/dex/quick/codegen_util.cc
+++ b/compiler/dex/quick/codegen_util.cc
@@ -929,6 +929,7 @@
 }
 
 void Mir2Lir::Materialize() {
+  cu_->NewTimingSplit("RegisterAllocation");
   CompilerInitializeRegAlloc();  // Needs to happen after SSA naming
 
   /* Allocate Registers using simple local allocation scheme */
@@ -940,6 +941,7 @@
        * special codegen doesn't succeed, first_lir_insn_ will
        * set to NULL;
        */
+      cu_->NewTimingSplit("SpecialMIR2LIR");
       SpecialMIR2LIR(mir_graph_->GetSpecialCase());
     }