commit a556e6ba500ba54d1ca90d6a947dd962d9c287c7
author Lena Djokic <Lena.Djokic@mips.com> Wed Dec 13 12:09:42 2017 +0100
committer Lena Djokic <Lena.Djokic@mips.com> Wed Jan 03 17:40:01 2018 +0100
tree f9e747c6218ca741c7b0783a9d10dedf22dd36b3
parent b0ddceb337f614dc2600d19b82fb4a6596aa7d4c

MIPS: InstructionCodeGeneratorMIPS*::DivRemByPowerOfTwo()

Replace [d]sll+[d]srl with [d]ins on R2+.

Change-Id: I7587e46c47c8ce413d81a5c6c29d91e32a14d855

compiler/optimizing/code_generator_mips.cc

diff --git a/compiler/optimizing/code_generator_mips.cc b/compiler/optimizing/code_generator_mips.cc
index 9f4c234..c4772ad 100644
--- a/compiler/optimizing/code_generator_mips.cc
+++ b/compiler/optimizing/code_generator_mips.cc
@@ -3774,8 +3774,12 @@
       if (IsUint<16>(abs_imm - 1)) {
         __ Andi(out, out, abs_imm - 1);
       } else {
-        __ Sll(out, out, 32 - ctz_imm);
-        __ Srl(out, out, 32 - ctz_imm);
+        if (codegen_->GetInstructionSetFeatures().IsMipsIsaRevGreaterThanEqual2()) {
+          __ Ins(out, ZERO, ctz_imm, 32 - ctz_imm);
+        } else {
+          __ Sll(out, out, 32 - ctz_imm);
+          __ Srl(out, out, 32 - ctz_imm);
+        }
       }
       __ Subu(out, out, TMP);
     }