Revert^2 "ART: Fix breaking changes from recent VIXL update."
This reverts commit eeaf47f7c9bbad29afab84a0f199a5751d9c616b.
Also fixes the gtest failure when VIXL simulator stack
was overflown.
Test: test-art-target, test-art-host.
Test: ART_USE_READ_BARRIER=false \
SANITIZE_HOST=address \
ASAN_OPTIONS='detect_leaks=0' \
SOONG_ALLOW_MISSING_DEPENDENCIES=true \
ART_HEAP_POISONING=true m test-art-host-gtest
Change-Id: Ibc1f21204940083879f767d6993127bdde8326af
diff --git a/compiler/optimizing/code_generator_arm64.cc b/compiler/optimizing/code_generator_arm64.cc
index 2de2cfb..f90c092 100644
--- a/compiler/optimizing/code_generator_arm64.cc
+++ b/compiler/optimizing/code_generator_arm64.cc
@@ -6913,11 +6913,11 @@
switch (kind) {
case BakerReadBarrierKind::kField:
case BakerReadBarrierKind::kAcquire: {
- auto base_reg =
- Register::GetXRegFromCode(BakerReadBarrierFirstRegField::Decode(encoded_data));
+ Register base_reg =
+ vixl::aarch64::XRegister(BakerReadBarrierFirstRegField::Decode(encoded_data));
CheckValidReg(base_reg.GetCode());
- auto holder_reg =
- Register::GetXRegFromCode(BakerReadBarrierSecondRegField::Decode(encoded_data));
+ Register holder_reg =
+ vixl::aarch64::XRegister(BakerReadBarrierSecondRegField::Decode(encoded_data));
CheckValidReg(holder_reg.GetCode());
UseScratchRegisterScope temps(assembler.GetVIXLAssembler());
temps.Exclude(ip0, ip1);
@@ -6963,8 +6963,8 @@
break;
}
case BakerReadBarrierKind::kArray: {
- auto base_reg =
- Register::GetXRegFromCode(BakerReadBarrierFirstRegField::Decode(encoded_data));
+ Register base_reg =
+ vixl::aarch64::XRegister(BakerReadBarrierFirstRegField::Decode(encoded_data));
CheckValidReg(base_reg.GetCode());
DCHECK_EQ(kBakerReadBarrierInvalidEncodedReg,
BakerReadBarrierSecondRegField::Decode(encoded_data));
@@ -6992,8 +6992,8 @@
// and it does not have a forwarding address), call the correct introspection entrypoint;
// otherwise return the reference (or the extracted forwarding address).
// There is no gray bit check for GC roots.
- auto root_reg =
- Register::GetWRegFromCode(BakerReadBarrierFirstRegField::Decode(encoded_data));
+ Register root_reg =
+ vixl::aarch64::WRegister(BakerReadBarrierFirstRegField::Decode(encoded_data));
CheckValidReg(root_reg.GetCode());
DCHECK_EQ(kBakerReadBarrierInvalidEncodedReg,
BakerReadBarrierSecondRegField::Decode(encoded_data));
diff --git a/compiler/optimizing/common_arm64.h b/compiler/optimizing/common_arm64.h
index 41f284f..d652492 100644
--- a/compiler/optimizing/common_arm64.h
+++ b/compiler/optimizing/common_arm64.h
@@ -65,12 +65,12 @@
inline vixl::aarch64::Register XRegisterFrom(Location location) {
DCHECK(location.IsRegister()) << location;
- return vixl::aarch64::Register::GetXRegFromCode(VIXLRegCodeFromART(location.reg()));
+ return vixl::aarch64::XRegister(VIXLRegCodeFromART(location.reg()));
}
inline vixl::aarch64::Register WRegisterFrom(Location location) {
DCHECK(location.IsRegister()) << location;
- return vixl::aarch64::Register::GetWRegFromCode(VIXLRegCodeFromART(location.reg()));
+ return vixl::aarch64::WRegister(VIXLRegCodeFromART(location.reg()));
}
inline vixl::aarch64::Register RegisterFrom(Location location, DataType::Type type) {
@@ -89,27 +89,27 @@
inline vixl::aarch64::VRegister DRegisterFrom(Location location) {
DCHECK(location.IsFpuRegister()) << location;
- return vixl::aarch64::VRegister::GetDRegFromCode(location.reg());
+ return vixl::aarch64::DRegister(location.reg());
}
inline vixl::aarch64::VRegister QRegisterFrom(Location location) {
DCHECK(location.IsFpuRegister()) << location;
- return vixl::aarch64::VRegister::GetQRegFromCode(location.reg());
+ return vixl::aarch64::QRegister(location.reg());
}
inline vixl::aarch64::VRegister VRegisterFrom(Location location) {
DCHECK(location.IsFpuRegister()) << location;
- return vixl::aarch64::VRegister::GetVRegFromCode(location.reg());
+ return vixl::aarch64::VRegister(location.reg());
}
inline vixl::aarch64::VRegister SRegisterFrom(Location location) {
DCHECK(location.IsFpuRegister()) << location;
- return vixl::aarch64::VRegister::GetSRegFromCode(location.reg());
+ return vixl::aarch64::SRegister(location.reg());
}
inline vixl::aarch64::VRegister HRegisterFrom(Location location) {
DCHECK(location.IsFpuRegister()) << location;
- return vixl::aarch64::VRegister::GetHRegFromCode(location.reg());
+ return vixl::aarch64::HRegister(location.reg());
}
inline vixl::aarch64::VRegister FPRegisterFrom(Location location, DataType::Type type) {
diff --git a/compiler/optimizing/intrinsics_arm64.cc b/compiler/optimizing/intrinsics_arm64.cc
index ee2fbd9..aa641e8 100644
--- a/compiler/optimizing/intrinsics_arm64.cc
+++ b/compiler/optimizing/intrinsics_arm64.cc
@@ -3082,16 +3082,16 @@
static void GenIsInfinite(LocationSummary* locations,
bool is64bit,
MacroAssembler* masm) {
- Operand infinity;
- Operand tst_mask;
+ Operand infinity(0);
+ Operand tst_mask(0);
Register out;
if (is64bit) {
- infinity = kPositiveInfinityDouble;
+ infinity = Operand(kPositiveInfinityDouble);
tst_mask = MaskLeastSignificant<uint64_t>(63);
out = XRegisterFrom(locations->Out());
} else {
- infinity = kPositiveInfinityFloat;
+ infinity = Operand(kPositiveInfinityFloat);
tst_mask = MaskLeastSignificant<uint32_t>(31);
out = WRegisterFrom(locations->Out());
}
diff --git a/compiler/optimizing/nodes_shared.cc b/compiler/optimizing/nodes_shared.cc
index 2f971b9..eca97d7 100644
--- a/compiler/optimizing/nodes_shared.cc
+++ b/compiler/optimizing/nodes_shared.cc
@@ -21,7 +21,7 @@
#include "nodes_shared.h"
-#include "common_arm64.h"
+#include "instruction_simplifier_shared.h"
namespace art {
diff --git a/compiler/utils/arm64/assembler_arm64.cc b/compiler/utils/arm64/assembler_arm64.cc
index d722e00..7ab767f 100644
--- a/compiler/utils/arm64/assembler_arm64.cc
+++ b/compiler/utils/arm64/assembler_arm64.cc
@@ -54,6 +54,9 @@
if (art_features->HasLSE()) {
features->Combine(vixl::CPUFeatures::kAtomics);
}
+ if (art_features->HasSVE()) {
+ features->Combine(vixl::CPUFeatures::kSVE);
+ }
}
Arm64Assembler::Arm64Assembler(ArenaAllocator* allocator,
diff --git a/compiler/utils/arm64/assembler_arm64.h b/compiler/utils/arm64/assembler_arm64.h
index 232efd4..5442b6a 100644
--- a/compiler/utils/arm64/assembler_arm64.h
+++ b/compiler/utils/arm64/assembler_arm64.h
@@ -144,7 +144,7 @@
} else if (code == XZR) {
return vixl::aarch64::xzr;
}
- return vixl::aarch64::Register::GetXRegFromCode(code);
+ return vixl::aarch64::XRegister(code);
}
static vixl::aarch64::Register reg_w(int code) {
@@ -154,15 +154,15 @@
} else if (code == WZR) {
return vixl::aarch64::wzr;
}
- return vixl::aarch64::Register::GetWRegFromCode(code);
+ return vixl::aarch64::WRegister(code);
}
static vixl::aarch64::VRegister reg_d(int code) {
- return vixl::aarch64::VRegister::GetDRegFromCode(code);
+ return vixl::aarch64::DRegister(code);
}
static vixl::aarch64::VRegister reg_s(int code) {
- return vixl::aarch64::VRegister::GetSRegFromCode(code);
+ return vixl::aarch64::SRegister(code);
}
private: