tree 5fc1e2e274bd455db829215dbf5e13350f32ddb2
parent a708e32a9f764a48175e705ec4bcd2201c84f492
author buzbee <buzbee@google.com> 1396036758 -0700
committer buzbee <buzbee@google.com> 1396036758 -0700

Quick compiler, MIPS resource cleanup

MIPS architecture includes internal registers HI and LO.
Similar to condition codes in other architectures, these internal
resouces must be accounted for during instruction scheduling.

Previously, the Quick backend for MIPS dealt with them by defining
rHI and rLO pseudo registers - treating them as actual registers for
def/use masks.  This CL changes the handling of these resources to
be in line with how condition codes are used elsewhere - leaving
register definitions to be used for registers.

Change-Id: Idcd77f3107b0c9b081ad05b1aab663fb9f41492d