Quick compiler, MIPS resource cleanup
MIPS architecture includes internal registers HI and LO.
Similar to condition codes in other architectures, these internal
resouces must be accounted for during instruction scheduling.
Previously, the Quick backend for MIPS dealt with them by defining
rHI and rLO pseudo registers - treating them as actual registers for
def/use masks. This CL changes the handling of these resources to
be in line with how condition codes are used elsewhere - leaving
register definitions to be used for registers.
Change-Id: Idcd77f3107b0c9b081ad05b1aab663fb9f41492d
diff --git a/compiler/dex/quick/mir_to_lir.h b/compiler/dex/quick/mir_to_lir.h
index bac35aa..c8ea25b 100644
--- a/compiler/dex/quick/mir_to_lir.h
+++ b/compiler/dex/quick/mir_to_lir.h
@@ -84,6 +84,10 @@
#define SETS_CCODES (1ULL << kSetsCCodes)
#define USES_CCODES (1ULL << kUsesCCodes)
#define USE_FP_STACK (1ULL << kUseFpStack)
+#define REG_USE_LO (1ULL << kUseLo)
+#define REG_USE_HI (1ULL << kUseHi)
+#define REG_DEF_LO (1ULL << kDefLo)
+#define REG_DEF_HI (1ULL << kDefHi)
// Common combo register usage patterns.
#define REG_DEF01 (REG_DEF0 | REG_DEF1)