ARM64: Move xSELF from x18 to x19.
This patch moves xSELF to callee saved x19 and removes support for
ETR (external thread register), previously used across native calls.
Change-Id: Icee07fbb9292425947f7de33d10a0ddf98c7899b
Signed-off-by: Serban Constantinescu <serban.constantinescu@linaro.org>
diff --git a/compiler/utils/arm64/assembler_arm64.cc b/compiler/utils/arm64/assembler_arm64.cc
index 98702a2..f924c71 100644
--- a/compiler/utils/arm64/assembler_arm64.cc
+++ b/compiler/utils/arm64/assembler_arm64.cc
@@ -52,11 +52,11 @@
}
void Arm64Assembler::GetCurrentThread(ManagedRegister tr) {
- ___ Mov(reg_x(tr.AsArm64().AsXRegister()), reg_x(ETR));
+ ___ Mov(reg_x(tr.AsArm64().AsXRegister()), reg_x(TR));
}
void Arm64Assembler::GetCurrentThread(FrameOffset offset, ManagedRegister /* scratch */) {
- StoreToOffset(ETR, SP, offset.Int32Value());
+ StoreToOffset(TR, SP, offset.Int32Value());
}
// See Arm64 PCS Section 5.2.2.1.
@@ -168,7 +168,7 @@
Arm64ManagedRegister scratch = m_scratch.AsArm64();
CHECK(scratch.IsXRegister()) << scratch;
LoadImmediate(scratch.AsXRegister(), imm);
- StoreToOffset(scratch.AsXRegister(), ETR, offs.Int32Value());
+ StoreToOffset(scratch.AsXRegister(), TR, offs.Int32Value());
}
void Arm64Assembler::StoreStackOffsetToThread64(ThreadOffset<8> tr_offs,
@@ -177,14 +177,14 @@
Arm64ManagedRegister scratch = m_scratch.AsArm64();
CHECK(scratch.IsXRegister()) << scratch;
AddConstant(scratch.AsXRegister(), SP, fr_offs.Int32Value());
- StoreToOffset(scratch.AsXRegister(), ETR, tr_offs.Int32Value());
+ StoreToOffset(scratch.AsXRegister(), TR, tr_offs.Int32Value());
}
void Arm64Assembler::StoreStackPointerToThread64(ThreadOffset<8> tr_offs) {
vixl::UseScratchRegisterScope temps(vixl_masm_);
vixl::Register temp = temps.AcquireX();
___ Mov(temp, reg_x(SP));
- ___ Str(temp, MEM_OP(reg_x(ETR), tr_offs.Int32Value()));
+ ___ Str(temp, MEM_OP(reg_x(TR), tr_offs.Int32Value()));
}
void Arm64Assembler::StoreSpanning(FrameOffset dest_off, ManagedRegister m_source,
@@ -285,7 +285,7 @@
}
void Arm64Assembler::LoadFromThread64(ManagedRegister m_dst, ThreadOffset<8> src, size_t size) {
- return Load(m_dst.AsArm64(), ETR, src.Int32Value(), size);
+ return Load(m_dst.AsArm64(), TR, src.Int32Value(), size);
}
void Arm64Assembler::LoadRef(ManagedRegister m_dst, FrameOffset offs) {
@@ -320,7 +320,7 @@
void Arm64Assembler::LoadRawPtrFromThread64(ManagedRegister m_dst, ThreadOffset<8> offs) {
Arm64ManagedRegister dst = m_dst.AsArm64();
CHECK(dst.IsXRegister()) << dst;
- LoadFromOffset(dst.AsXRegister(), ETR, offs.Int32Value());
+ LoadFromOffset(dst.AsXRegister(), TR, offs.Int32Value());
}
// Copying routines.
@@ -358,7 +358,7 @@
ManagedRegister m_scratch) {
Arm64ManagedRegister scratch = m_scratch.AsArm64();
CHECK(scratch.IsXRegister()) << scratch;
- LoadFromOffset(scratch.AsXRegister(), ETR, tr_offs.Int32Value());
+ LoadFromOffset(scratch.AsXRegister(), TR, tr_offs.Int32Value());
StoreToOffset(scratch.AsXRegister(), SP, fr_offs.Int32Value());
}
@@ -368,7 +368,7 @@
Arm64ManagedRegister scratch = m_scratch.AsArm64();
CHECK(scratch.IsXRegister()) << scratch;
LoadFromOffset(scratch.AsXRegister(), SP, fr_offs.Int32Value());
- StoreToOffset(scratch.AsXRegister(), ETR, tr_offs.Int32Value());
+ StoreToOffset(scratch.AsXRegister(), TR, tr_offs.Int32Value());
}
void Arm64Assembler::CopyRef(FrameOffset dest, FrameOffset src,
@@ -611,7 +611,7 @@
Arm64ManagedRegister scratch = m_scratch.AsArm64();
Arm64Exception *current_exception = new Arm64Exception(scratch, stack_adjust);
exception_blocks_.push_back(current_exception);
- LoadFromOffset(scratch.AsXRegister(), ETR, Thread::ExceptionOffset<8>().Int32Value());
+ LoadFromOffset(scratch.AsXRegister(), TR, Thread::ExceptionOffset<8>().Int32Value());
___ Cbnz(reg_x(scratch.AsXRegister()), current_exception->Entry());
}
@@ -628,12 +628,7 @@
// Pass exception object as argument.
// Don't care about preserving X0 as this won't return.
___ Mov(reg_x(X0), reg_x(exception->scratch_.AsXRegister()));
- ___ Ldr(temp, MEM_OP(reg_x(ETR), QUICK_ENTRYPOINT_OFFSET(8, pDeliverException).Int32Value()));
-
- // Move ETR(Callee saved) back to TR(Caller saved) reg. We use ETR on calls
- // to external functions that might trash TR. We do not need the original
- // ETR(X21) saved in BuildFrame().
- ___ Mov(reg_x(TR), reg_x(ETR));
+ ___ Ldr(temp, MEM_OP(reg_x(TR), QUICK_ENTRYPOINT_OFFSET(8, pDeliverException).Int32Value()));
___ Blr(temp);
// Call should never return.
@@ -714,12 +709,7 @@
SpillRegisters(core_reg_list, frame_size - core_reg_size);
SpillRegisters(fp_reg_list, frame_size - core_reg_size - fp_reg_size);
- // Note: This is specific to JNI method frame.
- // We will need to move TR(Caller saved in AAPCS) to ETR(Callee saved in AAPCS). The original
- // (ETR)X21 has been saved on stack. In this way, we can restore TR later.
- DCHECK(!core_reg_list.IncludesAliasOf(reg_x(TR)));
- DCHECK(core_reg_list.IncludesAliasOf(reg_x(ETR)));
- ___ Mov(reg_x(ETR), reg_x(TR));
+ DCHECK(core_reg_list.IncludesAliasOf(reg_x(TR)));
// Write StackReference<Method>.
DCHECK(X0 == method_reg.AsArm64().AsXRegister());
@@ -772,11 +762,7 @@
DCHECK_GE(frame_size, core_reg_size + fp_reg_size + sizeof(StackReference<mirror::ArtMethod>));
DCHECK_ALIGNED(frame_size, kStackAlignment);
- // Note: This is specific to JNI method frame.
- // Restore TR(Caller saved in AAPCS) from ETR(Callee saved in AAPCS).
- DCHECK(!core_reg_list.IncludesAliasOf(reg_x(TR)));
- DCHECK(core_reg_list.IncludesAliasOf(reg_x(ETR)));
- ___ Mov(reg_x(TR), reg_x(ETR));
+ DCHECK(core_reg_list.IncludesAliasOf(reg_x(TR)));
cfi_.RememberState();