commit 9b195cc7fc2bc81feb29fd8431a9f67204db1054
author Nicolas Geoffray <ngeoffray@google.com> Tue Apr 02 08:29:00 2019 +0100
committer Nicolas Geoffray <ngeoffray@google.com> Tue Apr 02 11:38:05 2019 +0000
tree a64255fe384de8ea6da67862aaf505cc495b92cf
parent 58412b1f6c6c1fb1f212dd4e2cb442541fc91df5

Fix arm32 code generator when used with baseline compilation.

A shift with zero can happen in baseline as we don't run
instruction simplification.

Also move baseline testing to AOT to catch such regressions.

Test: test.py --baseline
Change-Id: I9fa7af8e058135688ec44d907da7a6da27a6311e

compiler/optimizing/code_generator_arm_vixl.cc

diff --git a/compiler/optimizing/code_generator_arm_vixl.cc b/compiler/optimizing/code_generator_arm_vixl.cc
index c8db3d6..6469c69 100644
--- a/compiler/optimizing/code_generator_arm_vixl.cc
+++ b/compiler/optimizing/code_generator_arm_vixl.cc
@@ -4972,8 +4972,11 @@
             __ Lsrs(o_h, high, 1);
             __ Rrx(o_l, low);
           }
+        } else if (shift_value == 0) {
+          __ Mov(o_l, low);
+          __ Mov(o_h, high);
         } else {
-          DCHECK(0 <= shift_value && shift_value < 32) << shift_value;
+          DCHECK(0 < shift_value && shift_value < 32) << shift_value;
           if (op->IsShl()) {
             __ Lsl(o_h, high, shift_value);
             __ Orr(o_h, o_h, Operand(low, ShiftType::LSR, 32 - shift_value));