commit 9aebff2f19b605bff864308be51b604b7191163e
author Chris Larsen <chris.larsen@imgtec.com> Tue Sep 22 17:54:15 2015 -0700
committer Andreas Gampe <agampe@google.com> Mon Oct 19 08:14:04 2015 -0700
tree 78a49ebd0052617c3bd7d0bc17ec0b9d3fd206a0
parent a5903e622c0c11c1513a62e128a26d3cefd16c6f

MIPS64: Add intrinsic support for bit rotation

- int java.lang.Integer.rotateRight(int i, int distance)
- int java.lang.Long.rotateRight(long i, int distance)

Assembler tests for new MIPS instructions will be provided in a
separate patch.

Change-Id: I6dd4786e2d5f674bf56ff3d5afd321bb1bef589e

compiler/utils/mips64/assembler_mips64.cc

diff --git a/compiler/utils/mips64/assembler_mips64.cc b/compiler/utils/mips64/assembler_mips64.cc
index 7b4e6a3..00e8995 100644
--- a/compiler/utils/mips64/assembler_mips64.cc
+++ b/compiler/utils/mips64/assembler_mips64.cc
@@ -335,6 +335,10 @@
   EmitR(0, rs, rt, rd, 0, 0x04);
 }
 
+void Mips64Assembler::Rotrv(GpuRegister rd, GpuRegister rt, GpuRegister rs) {
+  EmitR(0, rs, rt, rd, 1, 0x06);
+}
+
 void Mips64Assembler::Srlv(GpuRegister rd, GpuRegister rt, GpuRegister rs) {
   EmitR(0, rs, rt, rd, 0, 0x06);
 }
@@ -351,6 +355,10 @@
   EmitR(0, static_cast<GpuRegister>(0), rt, rd, shamt, 0x3a);
 }
 
+void Mips64Assembler::Drotr(GpuRegister rd, GpuRegister rt, int shamt) {
+  EmitR(0, static_cast<GpuRegister>(1), rt, rd, shamt, 0x3a);
+}
+
 void Mips64Assembler::Dsra(GpuRegister rd, GpuRegister rt, int shamt) {
   EmitR(0, static_cast<GpuRegister>(0), rt, rd, shamt, 0x3b);
 }
@@ -363,6 +371,10 @@
   EmitR(0, static_cast<GpuRegister>(0), rt, rd, shamt, 0x3e);
 }
 
+void Mips64Assembler::Drotr32(GpuRegister rd, GpuRegister rt, int shamt) {
+  EmitR(0, static_cast<GpuRegister>(1), rt, rd, shamt, 0x3e);
+}
+
 void Mips64Assembler::Dsra32(GpuRegister rd, GpuRegister rt, int shamt) {
   EmitR(0, static_cast<GpuRegister>(0), rt, rd, shamt, 0x3f);
 }
@@ -375,6 +387,10 @@
   EmitR(0, rs, rt, rd, 0, 0x16);
 }
 
+void Mips64Assembler::Drotrv(GpuRegister rd, GpuRegister rt, GpuRegister rs) {
+  EmitR(0, rs, rt, rd, 1, 0x16);
+}
+
 void Mips64Assembler::Dsrav(GpuRegister rd, GpuRegister rt, GpuRegister rs) {
   EmitR(0, rs, rt, rd, 0, 0x17);
 }

compiler/utils/mips64/assembler_mips64.h

diff --git a/compiler/utils/mips64/assembler_mips64.h b/compiler/utils/mips64/assembler_mips64.h
index ac06521..33f22d2 100644
--- a/compiler/utils/mips64/assembler_mips64.h
+++ b/compiler/utils/mips64/assembler_mips64.h
@@ -123,15 +123,19 @@
   void Sra(GpuRegister rd, GpuRegister rt, int shamt);
   void Sllv(GpuRegister rd, GpuRegister rt, GpuRegister rs);
   void Srlv(GpuRegister rd, GpuRegister rt, GpuRegister rs);
+  void Rotrv(GpuRegister rd, GpuRegister rt, GpuRegister rs);
   void Srav(GpuRegister rd, GpuRegister rt, GpuRegister rs);
   void Dsll(GpuRegister rd, GpuRegister rt, int shamt);  // MIPS64
   void Dsrl(GpuRegister rd, GpuRegister rt, int shamt);  // MIPS64
+  void Drotr(GpuRegister rd, GpuRegister rt, int shamt);
   void Dsra(GpuRegister rd, GpuRegister rt, int shamt);  // MIPS64
   void Dsll32(GpuRegister rd, GpuRegister rt, int shamt);  // MIPS64
   void Dsrl32(GpuRegister rd, GpuRegister rt, int shamt);  // MIPS64
+  void Drotr32(GpuRegister rd, GpuRegister rt, int shamt);  // MIPS64
   void Dsra32(GpuRegister rd, GpuRegister rt, int shamt);  // MIPS64
   void Dsllv(GpuRegister rd, GpuRegister rt, GpuRegister rs);  // MIPS64
   void Dsrlv(GpuRegister rd, GpuRegister rt, GpuRegister rs);  // MIPS64
+  void Drotrv(GpuRegister rd, GpuRegister rt, GpuRegister rs);  // MIPS64
   void Dsrav(GpuRegister rd, GpuRegister rt, GpuRegister rs);  // MIPS64
 
   void Lb(GpuRegister rt, GpuRegister rs, uint16_t imm16);