| commit | 9adbff5b85fcae2b3e2443344415f6c17ea3ba0a | [log] [tgz] |
|---|---|---|
| author | Ian Rogers <irogers@google.com> | Wed Jan 23 18:19:03 2013 -0800 |
| committer | Ian Rogers <irogers@google.com> | Wed Jan 23 18:41:54 2013 -0800 |
| tree | e2893a0096a9c61f400d1f0bf0573eac75ae630d | |
| parent | cf07143e6b254a4087337d5f50bd7c1ee1b6a230 [diff] |
Implement Intel QuasiAtomics. Don't use striped locks for 64bit atomics on x86. Modify QuasiAtomic::Swap to be QuasiAtomic::Write that fits our current use of Swap and is closer to Intel's implementation. Return that MIPS doesn't support 64bit compare-and-exchanges in AtomicLong. Set the SSE2 flag for host and target Intel ART builds as our codegen assumes it. Change-Id: Ic1cd5c3b06838e42c6f94e0dd91e77a2d0bb5868